Semiconductor Memory Device Multi-Stage Verify Voltage Control
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in narrowing the threshold voltage distribution width of memory cells during programming operations, leading to inefficiencies and potential data loss.
Innovation Solution
The method involves performing multiple program loops with specific voltage settings for bit lines and word lines, including the use of pre-verify and main verify voltages to distinguish between program permission and prohibition cells, thereby controlling the threshold voltage movement widths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple verify voltages are used to distinguish program permission cells from program prohibition cells, then the threshold voltage distribution width is narrowed and programming precision is improved, but the operation complexity and time consumption increase
Solution Approach 1:
The verify operation is segmented into multiple stages with different verify voltages (first verify voltage, second verify voltage, third verify voltage) applied to different groups of memory cells. This segmentation allows systematic classification of cells into program permission and program prohibition groups, narrowing the threshold voltage distribution while managing complexity through structured multi-stage verification.
Solution Approach 2:
The patent applies preliminary verify operations using first and second verify voltages before the final program operation. These preliminary actions identify and separate program permission cells from program prohibition cells in advance, ensuring that only appropriate cells receive the main program voltage, thereby improving precision without unnecessarily increasing overall operation complexity.
2Productivity
If multiple verify voltages are applied to different bit lines, then programming efficiency is improved through accurate cell differentiation, but the operation time and control complexity increase
Solution Approach 1:
The verify operation is structured as periodic action with distinct phases: first verify operation with first verify voltage, second verify operation with second verify voltage, and third verify operation with third verify voltage. Each phase targets specific bit line groups systematically, improving programming efficiency through methodical cell differentiation while controlling operation time through structured periodic verification cycles.
Solution Approach 2:
Preliminary verify operations are performed before the main program operation to pre-identify program permission cells. This preliminary action prevents unnecessary programming attempts on prohibition cells, improving overall programming efficiency by ensuring accurate cell differentiation before committing to the full program sequence.
3Manufacturing precision
If different program permission voltages are applied to different bit lines, then threshold voltage movement control is improved, but the device control complexity increases
Solution Approach 1:
Different program permission voltages (first program permission voltage, second program permission voltage, third program permission voltage) are applied to different bit line groups based on local cell characteristics. This local quality approach allows precise control of threshold voltage movement for specific cell groups while maintaining manageable control complexity through systematic voltage assignment rules for different bit line groups.
Solution Approach 2:
The patent changes voltage parameters systematically across different verify and program operations. Different verify voltages and program permission voltages are applied based on cell state and bit line groupings, enabling precise threshold voltage movement control through parameter variation while maintaining structured control logic.
Data Source
AI summary
A method of operating a semiconductor memory device includes a plurality of program loops for programming selected memory cells among a plurality of memory cells. Each of the plurality of program loops includes setting a state of a bit line connected to the selected memory cells, applying a program voltage to a word line connected to the selected memory cells, and performing a verify operation on the selected memory cells using a first pre-verify voltage, a second pre-verify voltage greater than the first pre-verify voltage, and a main verify voltage greater than the second pre-verify voltage. A first program permission cell, a second program permission cell, a third program permission cell, and a program prohibition cell are determined by performing the verify operation.