Memory Devices with Different Sized Blocks of Memory Cells
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Solution Overview
Problem
Current memory devices, particularly NAND flash memory, face challenges in increasing memory density while maintaining efficient access times due to the high capacitance of control-gate plates in three-dimensional memory arrays, which slows down programming and reading operations.
Innovation Solution
The implementation of memory arrays with multiple block sizes, where smaller blocks have lower capacitance control-gate plates, allowing for faster programming and reading, and larger blocks with higher capacitance control-gate plates for storing frequently updated data, optimizing access times and power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional memory arrays with stacked memory cells are used to increase memory density, then memory density is improved, but access time deteriorates due to high capacitance of control-gate plates
Solution Approach 1:
The memory array is divided into multiple independent blocks, each with its own control-gate plate. This segmentation allows different blocks to have different capacitance values based on their size, enabling fast blocks (smaller capacitance) and slow blocks (larger capacitance) to coexist in the same three-dimensional memory structure, thus resolving the contradiction between high density and fast access.
Solution Approach 2:
Different blocks within the memory array are assigned different characteristics - specifically, different block sizes with corresponding different control-gate plate capacitances. Smaller blocks have lower capacitance for faster access, while larger blocks have higher capacitance for greater storage capacity. This local differentiation allows the system to optimize for both speed and density in different regions.
2Quantity of substance
If larger blocks with higher capacitance control-gate plates are used to store frequently updated data, then storage capacity is improved, but programming speed deteriorates
Solution Approach 1:
The system dynamically selects which block to use for programming operations based on the data characteristics and access patterns. Frequently updated data can be directed to smaller, faster blocks, while less frequently accessed data can utilize larger, higher-capacity blocks. This dynamic allocation optimizes both storage capacity utilization and programming speed.
Solution Approach 2:
The invention changes the parameter of block size to create a spectrum of options ranging from small fast blocks to large slow blocks. By varying the block size parameter, the system can match the programming speed and storage capacity requirements of different data types, resolving the contradiction between capacity and programming speed.
Data Source
AI summary
In an embodiment, each block of a plurality of blocks includes a respective plurality of strings of memory cells, where each of the plurality of strings of a block is coupled to a respective select transistor, and wherein each of the select transistors coupled to the plurality of strings of the block is coupled to a common first select line. The plurality of blocks includes N block sizes, where N may be an integer greater than or equal to three. N−1 blocks of one block size of the N block sizes collectively include a first number of second select lines. A group of blocks consisting of a respective block of each remaining block size of the N block sizes collectively include a second number of second select lines that is equal to the first number of select lines or that is less than the first number of second select lines.