Memory Die Identification Circuit Stack Position Detection
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Solution Overview
Problem
The increasing complexity and power consumption of electronic devices with enhanced functionality lead to challenges in managing power supply resources, performance degradation, and heat issues, particularly in memory devices with multiple chip-select specifications.
Innovation Solution
Implementing identification circuits with float detection or voltage detection circuits on each memory die to automatically determine its position in a stack and adjust chip-select routes or memory mapping, using through-substrate vias to couple with external chip-select connection nodes, allowing for uniform die design and efficient power distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory dies are stacked to increase storage capacity, then storage capacity is improved, but power consumption and heat generation increase
Solution Approach 1:
The memory system is divided into multiple independent memory dies stacked vertically, each die being a separate functional unit with its own identification circuit. This segmentation allows independent power management and operation for each die, enabling the system to achieve high storage capacity while managing power consumption through selective activation of individual dies based on their position and operational requirements
Solution Approach 2:
Each memory die includes an identification circuit that automatically detects its position in the stack and configures its own chip-select routing without external intervention. This self-service capability allows each die to adapt its operation independently, optimizing power usage by activating only the necessary components based on its detected position and operational needs
2Quantity of substance
If multiple memory dies are stacked to increase storage capacity, then storage capacity is improved, but heat generation increases leading to performance degradation
Solution Approach 1:
By segmenting the memory system into multiple vertically-stacked dies with independent identification and control circuits, heat generation is distributed across separate physical locations rather than concentrated in a single plane. This vertical segmentation improves thermal management by allowing heat to dissipate from each die independently
Solution Approach 2:
Each memory die is equipped with local identification circuits and position-detection capabilities that enable it to adapt its operational characteristics based on its specific location in the stack. This local quality approach allows each die to optimize its performance and power consumption according to its thermal environment and position-dependent requirements
3Adaptability or versatility
If identification circuits are added to each memory die to determine position, then adaptability is improved, but device complexity increases
Solution Approach 1:
The identification circuit is designed as a universal, multi-functional component that performs multiple tasks: detecting chip-select signal routing, determining die position in the stack, and configuring operational parameters. By consolidating these functions into a single circuit design that can be replicated across all dies, the patent achieves high adaptability without proportionally increasing overall system complexity
Solution Approach 2:
The same identification circuit design is copied and replicated on each memory die. This standardization allows each die to have identical adaptability capabilities while avoiding the complexity of designing unique control logic for each die. The copying approach enables position-based adaptation through a simple, repeatable circuit pattern that leverages the natural differences in signal routing based on die position
4Manufacturing precision
If through-substrate vias are used to couple memory dies, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent transitions from planar interconnect architecture to vertical three-dimensional interconnect architecture using through-substrate vias. This dimensional change allows signal routing to occur in the vertical dimension rather than requiring complex lateral routing, simplifying the interconnect architecture while achieving precise alignment through standardized via formation processes
Data Source
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AI summary
Memory die, stacks of memory dies, memory devices and methods, such as those to construct and operate such die, stacks and/or memory devices are provided. One such memory die includes an identification configured to be selectively coupled to an external select connection node depending on how the die is arranged in a stack. The identification circuit can determine an identification of its respective memory die responsive to how, if coupled, the identification circuit is coupled to the external select connection node.