Memory Die Stack Switching for Higher NAND I/O Bandwidth
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Solution Overview
Problem
Conventional bond wire architectures in NAND-type memory devices cause bandwidth restrictions in I/O data channels due to shared access among multiple memory dies in a stack.
Innovation Solution
A memory device with a stack of memory die packages, where each memory die package includes bonded memory dies, and a switch electrically coupled to the top surface of the memory die packages allows each memory die to have individual access to an I/O data channel through electrical connections and a bond wire to a substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If multiple memory dies share a common I/O data channel through conventional bond wire architecture, then device complexity is reduced and manufacturing is simplified, but bandwidth and electrical performance deteriorate due to shared access restrictions
Solution Approach 1:
The patent segments the shared I/O data channel into multiple dedicated channels, with each memory die having its own separate bond wire connection to the substrate. This segmentation eliminates the bandwidth bottleneck caused by shared access while maintaining manufacturing simplicity through standardized individual connections.
Solution Approach 2:
The patent introduces an intermediary switching mechanism between the memory dies and the substrate that enables selective connection of individual memory dies to the substrate. This intermediary allows each die to access the I/O channel independently when needed, resolving the bandwidth restriction without requiring permanent dedicated wiring to every die.
2Quantity of substance
If multiple memory dies are stacked in a single package, then storage capacity increases, but electrical performance and access speed deteriorate due to shared I/O channel contention
Solution Approach 1:
The patent segments the stacked memory die architecture by providing each die with separate electrical pathways to the substrate through individual bond wires. This segmentation allows simultaneous or rapid sequential access to multiple dies in the stack, eliminating the access speed degradation that would result from shared channel contention.
Solution Approach 2:
The patent implements dynamic switching capability that allows the system to selectively connect different memory dies to the I/O channel based on operational needs. This dynamic reconfiguration enables optimal access speed by directing I/O operations to the appropriate die without interference from other stacked dies.
3Manufacturing precision
If individual bond wires connect each pin cap on the substrate to each pin cap on memory dies, then manufacturing precision requirements are reduced, but bandwidth and electrical performance worsen due to shared channel limitations
Solution Approach 1:
The patent segments the electrical connection architecture into dedicated pathways for each memory die, with individual bond wires providing direct connections from substrate pin caps to corresponding die pin caps. This segmentation maintains relaxed manufacturing precision requirements while improving electrical performance by eliminating shared channel interference and signal degradation.
Data Source
AI summary
A memory device includes a stack of memory die packages. Each memory die package includes at least two memory dies. A switch is electrically coupled to at least one of the memory die packages. A bond wire electrically couples the switch to a substrate of the memory device. Each memory die is also electrically coupled to the switch. Based on a received control signal, the switch selects which memory die is electrically and/or communicatively coupled to the substrate using the electrical connections between the memory dies and the bond wire that electrically couples the switch to the substrate.