Memory Die Stacking via Redistribution Layers and Through Mold Vias
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Solution Overview
Problem
Current memory packaging solutions struggle to achieve high bandwidth and low latency while maintaining low capacity, often requiring high costs and complex technologies like through silicon via (TSV) stacking, which are expensive and power-intensive, and existing solutions for low capacity, high bandwidth needs are limited, leading to performance bottlenecks.
Innovation Solution
The development of electronic packages that enable high capacity memory packages through memory die stacking using redistribution layers, through mold vias, and passive silicon interposers, allowing for direct coupling of high bandwidth low latency (HBLL) memory dies to system-on-chip (SoC) dies via embedded multi-die interconnect bridges or on-die attach, reducing the need for high-cost HBM memory and TSVs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If through silicon via (TSV) stacking is used to achieve high bandwidth memory packages, then memory capacity and bandwidth are improved, but manufacturing cost and device complexity increase significantly
Solution Approach 1:
The patent introduces an interposer as an intermediary component between the logic die and memory dies. This interposer simplifies the connection architecture by providing a standardized interface layer, eliminating the need for complex direct TSV stacking between logic and memory components. The interposer handles the routing and signaling complexity, allowing simpler memory die designs to achieve high bandwidth performance.
Solution Approach 2:
The patent segments the memory package into separate functional components: a logic die, an interposer, and multiple memory dies. This segmentation allows each component to be optimized independently - the logic die for processing, the interposer for I/O connectivity, and the memory dies for storage capacity. This modular approach reduces overall system complexity while maintaining high bandwidth capabilities.
2Quantity of substance
If HBM memory packaging is used to achieve high capacity, then memory capacity is improved, but power consumption increases
Solution Approach 1:
The patent uses commodity HBM memory dies that are replicated and stacked to achieve the desired memory capacity. Rather than designing a custom high-capacity memory solution, the invention copies and stacks standardized memory dies, each optimized for low power consumption. This approach achieves high total capacity while maintaining low power consumption per bit, as each copied die operates in its optimal efficiency range.
3Quantity of substance
If off-chip high density memories are used to increase memory size, then memory capacity is improved, but operating speed and bandwidth are reduced
Solution Approach 1:
The patent transitions from two-dimensional off-chip memory connections to three-dimensional stacked memory architecture. By stacking memory dies vertically above the interposer, the invention achieves high memory capacity without increasing the horizontal footprint. This vertical dimensionality allows short interconnect lengths despite large memory capacity, maintaining high operating speed and bandwidth while achieving off-chip memory density benefits.
4Quantity of substance
If conventional DRAM with increased bank number is used to increase capacity, then memory capacity is improved, but die size and manufacturing cost increase
Solution Approach 1:
The patent uses vertical stacking to achieve memory capacity scaling without increasing die area. Instead of adding more banks horizontally on a single die (which increases die size), the invention stacks multiple memory dies vertically, each with a compact die area. This dimensional transition from horizontal to vertical scaling maintains small die sizes while achieving high total memory capacity.
Data Source
AI summary
Embodiments include electronic packages and methods of forming such packages. An electronic package includes a memory module comprising a first memory die. The first memory die includes first interconnects with a first pad pitch and second interconnects with a second pad pitch, where the second pad pitch is less than the first pad pitch. The memory module also includes a redistribution layer below the first memory die, and a second memory die below the redistribution layer, where the second memory die has first interconnects with a first pad pitch and second interconnects with a second pad pitch. The memory module further includes a mold encapsulating the second memory die, where through mold interconnects (TMIs) provide an electrical connection from the redistribution layer to mold layer. The TMIs may be through mold vias. The TMIs may be made through a passive interposer that is encapsulated in the mold.