Memory Device Distributing N-Bit Data Across Cells With Different Sensing Margins
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Solution Overview
Problem
Memory devices in neuromorphic systems and autonomous driving applications face limitations in operation logic calculation speed due to fixed data storage values in memory cells, which restricts the processing speed of neural network operations.
Innovation Solution
A memory device architecture that distributively stores N-bit data across M memory cells, where M is 2 or more, using different sensing margins for each cell, allowing the memory controller to read and process data efficiently by providing distinct reading voltages to each cell, thereby enhancing the calculation speed of operation logic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is stored in memory cells with fixed sensing margins, then manufacturing is simplified, but calculation speed of operation logic deteriorates due to inability to perform approximate computing
Solution Approach 1:
The patent applies local quality by configuring different memory cells with different sensing margins according to their functional requirements. Specifically, first memory cells store upper bits with larger sensing margins for high reliability, while second memory cells store lower bits with smaller sensing margins, enabling approximate computing without requiring all cells to have uniform high precision specifications.
2Productivity
If error detection processes are performed for all bits, then data reliability is improved, but processing speed deteriorates
Solution Approach 1:
The patent implements partial action by performing error detection only on upper bits stored in first memory cells with larger sensing margins, while omitting error detection for lower bits stored in second memory cells. This selective approach maintains sufficient reliability for critical data while improving overall processing speed by skipping redundant error checks on less critical lower bits.
3Productivity
If data is stored in a single memory cell, then device complexity is reduced, but calculation speed deteriorates due to sequential access requirements
Solution Approach 1:
The patent applies segmentation by dividing N-bit data into upper bits and lower bits, and storing them in separate first and second memory cells respectively. This allows the operation logic to access different bit portions from different memory cells simultaneously or in optimized sequences, improving calculation speed while the memory controller manages the distributed storage structure.
4Measurement precision
If reading voltages are optimized for each memory cell, then data read accuracy is improved, but control complexity increases
Solution Approach 1:
The patent implements parameter changes by applying different reading voltages to first and second memory cells based on their different sensing margins. The memory controller adjusts the reading voltage parameter according to which memory cell is being accessed and what type of data (upper bits or lower bits) is being read, thereby optimizing read accuracy for each cell type while the controller manages the voltage variation.
Data Source
AI summary
A memory device includes a memory cell array including M memory cells connected to one bit line and configured to distributively store N-bit data, where N is a natural number of 2 or more and M is a natural number of 2 or more and less than or equal to N, the M memory cells including a first memory cell and a second memory cell having different sensing margins, and a memory controller including a page buffer, the memory controller configured to distributively store the N-bit data in the M memory cells and to sequentially read data stored in the M memory cells to obtain the N-bit data, and an operation logic configured to execute an operation using the N-bit data, the memory controller configured to provide different reading voltages to the first memory cell and the second memory cell.