Memory DLL Load-Adaptive Delay Control for tAC Margin
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Solution Overview
Problem
Synchronous semiconductor memory devices face a decrease in clock access time margin (tAC) due to varying load magnitudes connected to data pins, leading to potential desynchronization of data output with external clock signals, especially as operating frequencies increase.
Innovation Solution
A DLL circuit with a transfer/delay circuit that adjusts the delay time of the feedback loop based on the load magnitude connected to the data pin, using serial presence detection and On Die Termination (ODT) circuit information to differentiate between single rank and double rank DIMMs, thereby maintaining valid data synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the delay time of the feedback loop is fixed for a single rank DIMM configuration, then the circuit design is simple, but the tAC margin decreases when a double rank DIMM is connected, causing data desynchronization
Solution Approach 1:
The patent implements a dynamic delay time adjustment mechanism in the DLL circuit that automatically adapts the feedback loop delay time based on the detected load magnitude. The transfer/delay circuit changes its delay characteristics according to whether a single rank or double rank DIMM is detected, ensuring optimal timing synchronization for each configuration without requiring separate fixed designs.
Solution Approach 2:
The patent changes the delay time parameter of the feedback loop based on the detected load configuration. By detecting the load magnitude through serial presence detection and ODT circuit information, the system adjusts the delay time parameter to compensate for the increased capacitive load of double rank DIMMs, thereby maintaining proper timing margins and data synchronization.
2Reliability
If the delay time is increased to accommodate double rank DIMM loads, then the tAC margin is maintained, but the clock access time increases, reducing operating speed
Solution Approach 1:
The system dynamically adjusts the delay time based on the actual load configuration rather than using a fixed conservative value. When a single rank DIMM is detected, the delay time is reduced to minimize access time and maximize speed. When a double rank DIMM is detected, the delay time is increased to maintain adequate tAC margin, thus optimizing performance for each specific configuration.
Solution Approach 2:
The delay time parameter is changed based on load detection results. By detecting whether a single rank or double rank DIMM is connected, the system adjusts the delay parameter accordingly - using a smaller delay for single rank to maximize speed and a larger delay for double rank to ensure reliability, thereby avoiding the need to always use the larger conservative delay value.
3Ease of manufacture
If the DLL circuit uses a fixed delay configuration, then the circuit is easier to manufacture, but it cannot adapt to different load magnitudes, causing synchronization failures
Solution Approach 1:
The patent introduces a dynamic adaptation mechanism that allows the DLL circuit to automatically adjust its delay characteristics based on the connected load. The transfer/delay circuit incorporates detection logic that identifies the load magnitude through serial presence detection and ODT circuit status, then dynamically reconfigures the delay time to match the specific DIMM configuration, enabling a single circuit design to handle both single and double rank DIMMs.
Solution Approach 2:
The DLL circuit performs self-configuration by automatically detecting the load magnitude through built-in detection mechanisms (serial presence detection and ODT circuit information) and adjusting its own delay parameters accordingly. This self-service capability eliminates the need for manual configuration or separate fixed designs for different DIMM types, allowing the circuit to adapt to its operating environment automatically.
Data Source
AI summary
A delay locked loop (DLL) circuit for a synchronous semiconductor memory device which can control a delay time of a feedback loop within the DLL circuit according to the magnitude of an external load, and a method of generating information about a load connected to a data pin of a synchronous semiconductor memory device are provided. The DLL circuit includes a replica output driver delaying an internal clock signal by a first delay time to output a first internal clock signal, the first delay time is a delay time of the internal clock signal which is generated by an output driver when a first load of a first magnitude is connected to an output terminal of the output driver, and a transfer/delay circuit transferring the first delay internal clock signal to a phase detector as a second delay internal clock signal when the first load is connected to the output terminal, and outputting the second delay internal clock signal to the phase detector by delaying the first delay internal clock signal by a second delay time, the second delay time is a delay time of the internal clock signal which is generated by the output driver when a second load of a second magnitude, which is larger than the first magnitude, is connected to the output terminal.