Memory DLL Output Control for Idle-State Power Reduction
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Solution Overview
Problem
Conventional delay locked loops (DLLs) in semiconductor memory devices experience unnecessary current consumption during active stand-by modes due to continuous toggling of DLL clocks, even when these clocks are not required, leading to inefficiencies in power management.
Innovation Solution
A semiconductor memory device with a DLL that includes an idle detector and an output controller, which generates a data section signal based on output data presence to control the DLL clock output, ensuring clocks are only supplied during active data output and turned off during idle or non-idle states, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the DLL continuously generates DLL clocks to ensure data synchronization, then the reliability of data output is improved, but the power consumption increases due to unnecessary clock toggling during idle or active-standby modes
Solution Approach 1:
The DLL clock output is made dynamic by introducing an output controller that adjusts the clock generation based on operational mode. During normal operation, the DLL generates clocks continuously for reliable synchronization. During idle or active-standby modes, the controller dynamically stops clock generation to reduce power consumption, thus adapting the system behavior to current operational requirements
Solution Approach 2:
The output controller receives feedback signals indicating the operational mode (normal, idle, or active-standby) and uses this feedback to control whether the DLL generates clocks. This feedback mechanism ensures that clocks are generated only when needed for data synchronization, eliminating unnecessary power consumption during modes where synchronization is not required
2Use of energy by moving object
If the DLL clock is turned off during idle modes to reduce power consumption, then the power consumption is reduced, but the data synchronization capability is lost when the clock is needed
Solution Approach 1:
The system dynamically transitions between clock generation and suspension based on operational mode. The output controller monitors mode signals and dynamically enables or disables the DLL clock output, ensuring that synchronization capability is restored immediately when transitioning from idle to normal operation mode
Solution Approach 2:
The output controller is designed to restore DLL clock generation quickly upon detecting a transition from idle or active-standby mode to normal operation mode. This preliminary preparation ensures that synchronization capability is re-established without delay, maintaining data output reliability
Data Source
AI summary
A semiconductor memory device has a delay locked loop (DLL) with low power consumption. The semiconductor memory device includes a DLL for receiving an external clock to generate a DLL clock, an idle detector for detecting an idle state in which a command for driving a device is not supplied, and an output controller for controlling the output of the DLL through the idle state whether or not data is output.