Memory DQ Swapping Circuit for Error Correction After Data Remapping
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Solution Overview
Problem
Memory module designs that prioritize routing efficiency and signal integrity often re-map data terminals in a most-significant-bit to least-significant-bit order, which compromises the host's ability to perform effective error correction, reducing the reliability and robustness of the memory module.
Innovation Solution
Implementing DQ mapping circuits within memory packages and hosts to rearrange data terminals, either within the memory module or at the host level, to circumvent the swizzle mapping and restore the original data order, thereby facilitating more robust error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data terminals are re-mapped in MSB to LSB order for routing efficiency and signal integrity, then routing efficiency and signal integrity are improved, but error correction capability deteriorates
Solution Approach 1:
The patent applies preliminary action by performing DQ swapping at the memory package level before data exits the memory module. The swizzle circuit re-arranges data bits in a predetermined pattern that compensates for the MSB-to-LSB re-mapping, ensuring that data presented to the host is in the correct order for error correction operations without requiring the host to perform additional re-arrangement
Solution Approach 2:
The patent introduces an intermediary swizzle circuit within the memory package that acts as a mediator between the memory array and the external interface. This circuit performs the necessary bit re-arrangement and DQ swapping, decoupling the internal data organization from the external routing requirements, thereby maintaining both routing efficiency and error correction capability
2Reliability
If DQ swapping is performed at the host level, then error correction capability is improved, but host complexity increases
Solution Approach 1:
The patent extracts the DQ swapping functionality from the host system and relocates it to the memory package level. The swizzle circuit is integrated into the memory package, separating the data re-arrangement function from the host processor, thereby improving error correction capability without increasing host complexity
Solution Approach 2:
The memory package performs self-service by implementing the swizzle circuit within itself, autonomously handling the data bit re-arrangement and DQ swapping required for proper error correction. This eliminates the need for the host to implement additional complexity to achieve the same goal
Data Source
AI summary
An exemplary memory includes a first sub-wordline (SWL) driver configured to provide first data from a memory cell array, a second SWL driver configured to provide second data from a memory cell array, and an input/output (I/O) circuit configured to receive the first data and the second data from the first and second SWL drivers, respectively. The I/O circuit including a data terminal mapping circuit configured to selectively route the first data and the second data to different respective data terminal based on a data terminal mapping setting.