Memory Device ECC Engine and Row Fail Detector for Error Management
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Solution Overview
Problem
Existing memory devices face challenges in efficiently detecting and correcting errors, particularly in identifying fail rows within the memory cell array, which can impact data reliability and system performance.
Innovation Solution
The proposed memory device incorporates an ECC engine for error detection and correction, a row fail detector to identify fail rows, and a flag generator to produce decoding state and fail row flags, enabling effective error management and row failure detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If process scale is reduced to increase degree of integration, then productivity and integration density improve, but error occurrence rate increases
Solution Approach 1:
The patent applies preliminary action by performing periodic row failure detection and data correction before errors actually occur or propagate. The memory device proactively identifies fail rows through detection operations and corrects potential errors by storing corrected data in replacement rows, preventing future read errors and maintaining data integrity despite process scaling challenges.
2Reliability
If row failure detection and correction mechanisms are added, then reliability improves, but device complexity increases
Solution Approach 1:
The patent segments the error handling function into distinct modular components: a row fail detector that identifies fail rows, an ECC engine that corrects errors, and a replacement row manager that handles data relocation. This segmentation allows each component to perform its specific function independently, improving reliability while keeping the overall system manageable through functional decomposition.
Solution Approach 2:
The memory device structure is designed with multi-functionality where the same memory cell array serves both as storage for normal data and as a pool for replacement rows. The ECC engine and row fail detector work together to provide both detection and correction functions using shared resources, reducing overall device complexity while maintaining comprehensive error handling capabilities.
Data Source
AI summary
A memory device includes a memory cell array including memory cells arranged in a plurality of rows; an ECC engine configured to detect an error in first data that is read from the memory cell array in response to a read command and a read address, to output a first error occurrence signal, and to correct the error in the first data; a row fail detector configured to output a fail row address, which indicates a fail row among the plurality of rows; and a flag generator configured to receive the read address, the first error occurrence signal, and the fail row address, and to generate a decoding state flag, which indicates whether an error is detected and whether an error is corrected, and a fail row flag, which indicates that a read row address included in the read address is the fail row address.