Memory System ECC Storage Segmentation for Bandwidth Efficiency
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Solution Overview
Problem
Existing memory systems face bandwidth degradation due to error correcting code (ECC) inefficiencies, particularly in temporal multiplexing, which requires additional memory and degrades memory system performance.
Innovation Solution
The memory system design includes separate independently addressable storage regions for data and ECC, with dedicated row decoders and column I/Os, allowing concurrent access and storage of data and ECC, optimizing bandwidth usage through partial word-line activations and multiplexing mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If temporal multiplexing is used to communicate ECCs with data signals via shared datapaths, then memory device complexity is reduced, but memory system bandwidth is degraded
Solution Approach 1:
The memory device is divided into two independently addressable storage regions: a first storage region for data and a second storage region for ECCs. Each region has its own dedicated row decoder and column I/Os, allowing simultaneous independent access to both data and ECCs without temporal multiplexing, thus maintaining full bandwidth while reducing device complexity.
Solution Approach 2:
Instead of using temporal multiplexing (time dimension) to share datapaths, the invention uses spatial separation by creating independent storage regions with dedicated decoders and I/Os. This dimensional shift from time-based sharing to space-based separation allows concurrent access without bandwidth degradation.
2Reliability
If additional memory is allocated for ECC storage, then error detection and correction capability is improved, but memory system bandwidth is degraded
Solution Approach 1:
The memory device is segmented into two independently addressable storage regions: a first storage region for data and a second storage region for ECCs. Each region has dedicated row decoders and column I/Os, enabling simultaneous independent access. This segmentation allows full utilization of memory bandwidth for both data and ECC operations without degradation, while maintaining comprehensive error detection and correction capability.
3Productivity
If separate independently addressable storage regions with dedicated row decoders and column I/Os are used for data and ECC, then memory system bandwidth efficiency is improved, but device complexity is increased
Solution Approach 1:
The memory device is segmented into two independently addressable storage regions with dedicated row decoders and column I/Os for each region. This segmentation enables concurrent access to data and ECCs, fully utilizing memory bandwidth without the degradation caused by temporal multiplexing. The increased device complexity is offset by the elimination of multiplexing logic and the ability to perform simultaneous operations.
Solution Approach 2:
Each storage region is designed to be independently addressable and functional, allowing the memory device to handle data and ECC operations simultaneously through separate pathways. This multi-functionality enables the system to maintain high bandwidth efficiency while providing comprehensive error detection and correction capabilities.
Data Source
AI summary
The disclosed embodiments relate to components of a memory system that support error detection and correction by means of storage and retrieval of error correcting codes. In specific embodiments, this memory system includes a memory device, which further contains a memory bank. During operation, the memory device receives a request to concurrently access a data word at a first row in a first storage region of the memory bank and error information associated with the data at a second row in a second storage region of the memory bank. Moreover, the memory request includes a first row address identifying the first row and a second row address identifying the second row. Next, the memory device routes the first row address and the second row address to a first row decoder and a second row decoder in the memory bank, respectively. Finally, the memory device uses the first row decoder to decode the first row address to access the first row and concurrently uses the second row decoder to decode the second row address to access the second row.