3D Stacked Memory ECC Striping With Parity Vault Recovery
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Solution Overview
Problem
Current memory systems face challenges in efficiently managing increased complexity and power consumption while ensuring data integrity, particularly in handling single and multi-bit errors across multiple memory chips, as more complex error correction schemes require additional memory and chip area.
Innovation Solution
The memory device employs a 3D stack architecture with memory vaults that share common control logic, using a parity vault system for error correction, where data is striped across multiple vaults for redundancy, and a DMA engine rebuilds faulty vaults transparently to the user, enhancing energy efficiency and error correction capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If more complex error correction schemes are implemented, then data integrity is improved, but additional memory and chip area are required
Solution Approach 1:
The patent combines multiple error correction capabilities (single-bit correction, multi-bit detection, and chip failure protection) into a unified ECC scheme that operates across stacked memory chips. The ECC data is distributed across multiple chips in the stack, allowing the system to correct errors without requiring separate dedicated correction memory for each chip type
Solution Approach 2:
The ECC scheme is designed to handle multiple types of errors simultaneously using the same hardware infrastructure. The same ECC data and correction logic protect against single-bit errors, multi-bit errors, and complete chip failures, eliminating the need for separate correction systems for each error type
2Reliability
If error correction data is scattered across multiple memory chips, then protection against chip failure is improved, but device complexity increases
Solution Approach 1:
The patent divides the memory stack into multiple independently addressable chips, each containing portions of the data and ECC information. This segmentation allows any single chip to fail without compromising the entire system, as the remaining chips contain sufficient information to reconstruct the data
Solution Approach 2:
Error correction data is pre-distributed across multiple chips during the memory initialization phase. This preliminary distribution ensures that when a chip fails, the correction information is already in place on other chips, eliminating the need for complex real-time calculation during error recovery
3Quantity of substance
If memory capacity increases, then storage capability is improved, but power consumption increases
Solution Approach 1:
The patent transitions from traditional 2D memory expansion to 3D stacked architecture, where multiple memory chips are vertically stacked and interconnected. This dimensional change allows significant capacity increases without proportional increases in chip area or power consumption, as the stack shares common control logic and interconnect structures
Data Source
AI summary
Electronic apparatus, systems, and methods to construct and operate the electronic apparatus and/or systems include a stack of memory dies with user data and/or first level error correction data stored in a stripe across the memory dies. One such stack can include a second level error correction vault, such as a parity vault, to store parity data corresponding to the user data and/or first level error correction data. Additional apparatus, systems, and methods are disclosed.