Memory Sub-System ECC Access for Weak Device Latency Reduction
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Solution Overview
Problem
Memory access operations at memory cells with specific characteristics or in weak memory devices frequently fail, leading to increased latency and decreased efficiency in memory sub-systems due to the need for multiple error correction operations.
Innovation Solution
A memory sub-system controller determines whether memory cells satisfy cell degradation criteria or reside in weak memory devices, and performs an initial error correction operation instead of a memory access operation to reduce latency, selecting subsequent operations based on cell characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction operations are performed to access data in weak memory devices or degraded memory cells, then data access reliability is improved, but operation latency increases
Solution Approach 1:
The system performs preliminary characterization of memory devices and cells during manufacturing or initial operation to identify weak devices and degraded cells. This preliminary action creates a database of memory characteristics that enables the controller to proactively select appropriate error correction operations before actual data access failures occur, thereby improving reliability without incurring latency penalties during normal operation.
Solution Approach 2:
The error correction mechanism dynamically adapts its operation based on real-time memory cell characteristics and degradation states. The controller selects from multiple error correction operations (e.g., different ECC codes, read retry strategies, or voltage adjustment levels) depending on the specific memory cell's properties, optimizing the balance between reliability improvement and latency minimization for each individual access operation.
2Reliability
If multiple error correction operations are performed to access data in degraded memory cells, then data access reliability is improved, but the number of operations increases
Solution Approach 1:
The system performs preliminary characterization of memory devices and cells during manufacturing or initial operation to identify weak devices and degraded cells. This preliminary action creates a database of memory characteristics that enables the controller to proactively select appropriate error correction operations before actual data access failures occur, thereby improving reliability without incurring latency penalties during normal operation.
Solution Approach 2:
The error correction mechanism applies different correction strategies tailored to specific memory cells' degradation characteristics rather than using a uniform approach for all cells. By analyzing individual cell properties (such as threshold voltage shifts, program/erase cycle counts, or previous error patterns), the system applies only the necessary level of error correction for each cell, minimizing the number of operations required while maintaining high reliability.
3Productivity
If error correction operations are selectively applied based on memory cell characteristics, then operation efficiency is improved, but device complexity increases
Solution Approach 1:
The system performs preliminary characterization of memory devices and cells during manufacturing or initial operation to identify weak devices and degraded cells. This preliminary action creates a database of memory characteristics that enables the controller to proactively select appropriate error correction operations before actual data access failures occur, thereby improving reliability without incurring latency penalties during normal operation.
Solution Approach 2:
The controller maintains a copy or lookup table of memory cell characteristics and appropriate error correction strategies, allowing it to quickly reference and apply the correct correction operation without performing complex real-time analysis. This copying approach simplifies the controller's real-time decision-making process while maintaining high operation efficiency through pre-computed correction mappings.
Data Source
AI summary
A request to access data programmed to a memory sub-system is received. A determination is made of whether a memory device that stores the data referenced by the request satisfies a weak memory device criterion in view of a quality rating for the device. In response to a determination that the memory device satisfies the weak memory device criterion, an error correction operation to access the data is performed in accordance with the request.