3D Memory Erase Bias Sequencing to Prevent Hot Carrier Injection
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Solution Overview
Problem
In three-dimensional memory devices with vertical channel structures, the hot carrier injection (HCI) phenomenon occurs during erase operations, particularly affecting the ground erase control transistor, leading to inefficiencies and potential damage.
Innovation Solution
The implementation of a bias voltage application strategy during the erase setup period, where a first bias voltage is applied to word lines and dummy word lines connected to memory cells near the ground erase control transistor, followed by a second, lower bias voltage after the first period, before the common source line reaches the erase voltage level, to prevent HCI.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a high voltage is applied to the common source line during erase operation to enable efficient erasing, then the erase operation efficiency is improved, but the hot carrier injection (HCI) phenomenon occurs in the ground erase control transistor causing potential damage and reduced reliability
Solution Approach 1:
The patent applies a first bias voltage to the first word lines and dummy word lines before the common source line voltage reaches the erase voltage level (during the erase setup period). This preliminary action prepares the channel potential in advance, preventing HCI phenomenon from occurring when the high erase voltage is subsequently applied to the common source line, thus protecting the ground erase control transistor while maintaining erase efficiency
Solution Approach 2:
The patent dynamically changes the bias voltage parameters applied to different word lines based on their position relative to the ground erase control transistor. First word lines (closer to the ground erase control transistor) receive a first bias voltage during the erase setup period, while second word lines (farther away) receive a second bias voltage. This parameter differentiation optimizes the channel potential distribution to prevent HCI in the ground erase control transistor while enabling efficient erasing
2Reliability
If a bias voltage is applied to all word lines during the erase setup period to prevent HCI, then the reliability of the ground erase control transistor is improved, but the complexity of the voltage control increases
Solution Approach 1:
The patent segments the word lines into two groups: first word lines connected to memory cells relatively close to the ground erase control transistor, and second word lines connected to memory cells relatively far from the ground erase control transistor. This segmentation allows differential bias voltage application, where only the first word lines require special bias voltage control during the erase setup period, while the second word lines use a different bias voltage scheme, thereby reducing overall control complexity compared to uniform biasing of all word lines
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces or prevents the HCI phenomenon, enhancing the reliability and efficiency of erase operations in memory devices by minimizing channel injection of holes.
Implementation Method 1
the hot carrier injection (HCI) phenomenon occurs during erase operations, particularly affecting the ground erase control transistor
Implementation Method 2
a three-dimensional memory device including a plurality of vertical channel structures extending in a vertical direction on a substrate has been developed
Data Source
AI summary
A memory device includes a memory cell array including a plurality of cell strings each extending in a vertical direction on a substrate. A plurality of word lines include first word lines connected to memory cells relatively close to the ground erase control transistor and second word lines connected to memory cells relatively far from the ground erase control transistor and a row decoder configured to apply a first bias voltage to the first word lines and the dummy word lines in a first period of an erase setup period, and a second bias voltage at a level lower than a level of the first bias voltage to the first word lines and the dummy word line in a second period during the erase setup period. The second period starts before the level of the voltage applied to the common source line reaches the erase voltage level.