Semiconductor Memory Erase Voltage Pulse Width Control
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Solution Overview
Problem
In three-dimensional semiconductor memory devices, the erase operation is hindered by a phenomenon where the threshold voltage of memory cells can rise due to hole de-trapping and electron back-tunneling, leading to saturation and inefficient data erasure, especially when the pulse width of the erase voltage is prolonged.
Innovation Solution
The semiconductor memory device employs a control unit that adjusts the erase voltage by increasing its value and shortening the pulse width during the second stage of the erase operation, compared to the first stage, to prevent threshold voltage saturation and promote efficient data erasure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the pulse width of the erase voltage is prolonged to ensure complete data erasure, then the erasure completeness is improved, but the threshold voltage of memory cells rises due to hole de-trapping and electron back-tunneling, causing operation saturation
Solution Approach 1:
The erase operation is divided into multiple stages with different pulse widths. In the first stage, a longer pulse width is used to ensure complete erasure of strongly retained charges. In the second stage, a shorter pulse width is used to complete the erasure of remaining charges without causing excessive threshold voltage rise. This segmentation allows the system to achieve complete erasure while minimizing harmful threshold voltage effects.
Solution Approach 2:
The pulse width of the erase voltage is dynamically adjusted based on the erasure stage. The control unit changes the pulse width from longer in the first stage to shorter in the second stage, optimizing the erasure process at each phase. This dynamic adjustment ensures that the erase operation is both complete and efficient, preventing threshold voltage saturation.
2Reliability
If the erase voltage is applied with a long pulse width to erase all data, then the data erasure completeness is improved, but the erase operation time increases and efficiency decreases
Solution Approach 1:
The erase operation is segmented into two stages with different pulse widths. The first stage uses a longer pulse width to address strongly retained charges, while the second stage uses a shorter pulse width to handle remaining charges. This segmentation reduces the total erase time compared to using a single long pulse width, as the second stage can be terminated earlier when sufficient erasure is achieved.
Solution Approach 2:
In the second stage, a shorter pulse width is applied that may not be sufficient for complete erasure of all charge types, but it is optimized for the remaining charges after the first stage. This partial action approach allows the system to achieve practical erasure completeness without the time penalty of a uniformly long pulse width throughout the entire operation.
3Object-generated harmful factors
If the threshold voltage of memory cells is allowed to rise during erase operation, then hole de-trapping and electron back-tunneling are reduced, but the erase operation becomes inefficient and data erasure is incomplete
Solution Approach 1:
The control unit dynamically adjusts the pulse width of the erase voltage based on the erasure stage. By shortening the pulse width in the second stage, the system maintains lower threshold voltage levels, preventing excessive hole de-trapping and electron back-tunneling. This dynamic control ensures efficient erasure operation while minimizing harmful voltage effects.
Solution Approach 2:
The pulse width parameter of the erase voltage is changed between stages. The control unit sets a longer pulse width for the first stage to ensure complete erasure, then switches to a shorter pulse width for the second stage. This parameter change optimizes the balance between erasure completeness and preventing threshold voltage rise, thereby maintaining high erase operation efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach speeds up the erase operation while preventing the threshold voltage from rising, ensuring effective data erasure and maintaining the integrity of the memory cells.
Implementation Method 1
a phenomenon where the threshold voltage of memory cells can rise due to hole de-trapping and electron back-tunneling
Implementation Method 2
a phenomenon where the threshold voltage of memory cells can rise due to hole de-trapping and electron back-tunneling
Data Source
AI summary
A semiconductor memory device according to an embodiment includes: a memory cell array including a plurality of charge accumulation type memory cells; and a control unit that controls the memory cell array. The control unit, when executing an erase operation on the memory cell array, applies an erase voltage to the memory cells. The erase voltage is a voltage in a pulse form. The control unit performs control that, compared to when the erase operation is in a first stage, increases a voltage value and shortens a pulse width of the erase voltage when the erase operation is in a second stage.