Non-volatile Memory Erase Control via Segmented Pass Transistors
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Solution Overview
Problem
Non-volatile memory devices with multi-hole structures experience performance variations due to differences in intrinsic characteristics of channel holes, leading to inconsistent erase operations.
Innovation Solution
A non-volatile memory device design that includes a plurality of word lines stacked vertically, with erase control lines grouped into distinct groups based on proximity to a word line cut region, utilizing pass transistors to apply different erase control voltages to each group, allowing for controlled voltage levels and application times to optimize erase operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If individual pass transistors are provided for each erase control line, then erase operation precision is improved, but device complexity and chip size increase
Solution Approach 1:
The erase control lines are divided into multiple groups (first group, second group, etc.) based on their spatial location relative to the word line cut region. Each group is assigned a dedicated pass transistor, rather than providing individual transistors for each line. This segmentation approach reduces the total number of pass transistors while maintaining sufficient control precision for each group.
Solution Approach 2:
Multiple erase control lines that are spatially adjacent or have similar characteristics are merged into the same group and controlled by a common pass transistor. This merging reduces the overall number of pass transistors required in the device, thereby reducing device complexity and chip size while still achieving effective erase control.
2Ease of operation
If more pass transistors are used for each erase control line, then erase operation control is improved, but chip size increases
Solution Approach 1:
The erase control lines are segmented into multiple groups based on their spatial location, with each group controlled by a dedicated pass transistor. This segmentation provides sufficient operational control for each group while avoiding the need for individual transistors for every single line, thus controlling chip size.
Solution Approach 2:
Different groups of erase control lines are controlled with different levels of granularity. Lines in the same group share a common pass transistor, while different groups have different pass transistors. This local quality approach optimizes the balance between control precision and chip area by applying different control strategies to different spatial regions.
3Productivity
If channel holes are increased to improve integration degree, then memory capacity is improved, but performance variation due to intrinsic characteristics increases
Solution Approach 1:
The patent applies different control strategies to different spatial regions by dividing erase control lines into groups based on their location relative to the word line cut region. This local quality approach compensates for the intrinsic characteristic variations of channel holes in different regions, thereby maintaining performance consistency even as the number of channel holes increases for higher memory capacity.
Solution Approach 2:
The patent changes the control parameters (voltage levels, application times) of erase control voltages applied to different groups of erase control lines. By adjusting these parameters based on the spatial location and intrinsic characteristics of channel holes in each region, the patent achieves consistent erase performance across all channel holes, even as the total number of channel holes increases to improve memory capacity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces performance variations by improving erase efficiency and maximizing GIDL current, while minimizing chip size and reducing the need for individual pass transistors for each erase control line.
Implementation Method 1
maximizing GIDL current
Data Source
AI summary
A non-volatile memory device includes a plurality of word lines stacked above a substrate in a vertical direction; erase control lines that are spaced apart from each other in a first direction and extend in a second direction; a pass transistor circuit including a first pass transistor connected to a first group of erase control lines and a second pass transistor connected to a second group of erase control lines; and a memory cell array including a plurality of blocks. The first group of erase control lines are relatively close to a word line cut region and the second group of erase control lines are relatively far from the word line cut region. Each of the plurality of blocks includes a plurality of channel structures connected to the word lines and the erase control lines and each channel structure extends in the vertical direction.