Nonvolatile Memory Erase Control via Soft Program Operations
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Solution Overview
Problem
The existing nonvolatile memory apparatuses face reliability issues due to a wide threshold voltage distribution during erase operations, which increases program operation time and degrades memory performance.
Innovation Solution
A memory apparatus and method that control an erase operation by performing a first soft program operation to adjust threshold voltage distribution and a second soft program operation to narrow the distribution, using a control logic unit and voltage generating unit to apply specific voltage levels to word lines, ensuring cells are erased to a precise voltage level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional erase operation is performed, then memory cells are erased, but the threshold voltage distribution becomes wide and excessive erosion occurs in some cells
Solution Approach 1:
The erase operation is divided into multiple stages: a first erase operation to erase memory cells, and a second erase operation to specifically target and re-erase cells that were excessively erased in the first operation. This segmentation allows precise control over the threshold voltage distribution and prevents excessive erosion while maintaining uniformity across all cells.
Solution Approach 2:
A verify operation is performed after the first erase operation to detect the threshold voltage distribution of erased cells. Based on the verification results, the control logic unit determines whether a second erase operation is needed, creating a feedback loop that adjusts the erase process to achieve uniform threshold voltage distribution and prevent excessive erosion.
2Reliability
If Soft program On Chip (SOC) operation is performed to correct threshold voltage distribution, then threshold voltage distribution is adjusted to erase voltage level, but the width of threshold voltage distribution cannot be reduced
Solution Approach 1:
The correction process is segmented into two distinct operations: the first Soft program On Chip operation to adjust threshold voltage distribution to the erase voltage level, and the second Soft program On Chip operation specifically to reduce the width of the threshold voltage distribution. This segmentation enables both accuracy and precision improvements that cannot be achieved through a single operation.
Solution Approach 2:
The patent applies different voltage levels dynamically across two sequential Soft program On Chip operations. The first operation uses a first voltage level to adjust the distribution, while the second operation uses a second voltage level (different from the first) to narrow the distribution width, enabling adaptive control over the threshold voltage characteristics.
3Reliability
If the width of threshold voltage distribution of erased cells is not sufficiently narrowed, then program operation time increases and interference increases
Solution Approach 1:
The second Soft program On Chip operation is performed as a preliminary action before subsequent program operations to narrow the threshold voltage distribution width. By proactively reducing the distribution width after the erase operation, the patent prevents future program operation delays and interference issues, ensuring efficient subsequent operations without requiring extended correction time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively narrows the threshold voltage distribution, reducing interference and enhancing the reliability of the nonvolatile memory apparatus by optimizing the erase operation.
Implementation Method 1
In an erase operation, a low gate voltage is applied to a control gate to extract electrons that were injected into a floating gate by the F-N tunneling effect
Data Source
AI summary
An erase operation of a memory apparatus is controlled by, inter alia, selecting one or more memory cell blocks to be erased among a plurality of memory cell blocks, performing an erase operation on the selected one or more memory cell blocks in response to an erase command, performing a first soft program operation on the selected one or more memory cell blocks if the erase operation is determined as passed, and performing a second soft program operation on the selected one or more memory cell blocks if the first soft program operation is determined as passed.