Nonvolatile Memory Erase Voltage Control Circuit
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Solution Overview
Problem
Current nonvolatile memory devices face challenges in effectively controlling voltages during the erase operation, particularly in preventing ground and string selection transistors from entering quasi-on or turn-on states, which can lead to programming or erasure issues.
Innovation Solution
The proposed solution involves a method for controlling the voltages of ground selection lines and string selection lines by maintaining a predetermined voltage difference and controlling the rising and falling slopes of these voltages relative to the substrate voltage, using a voltage generating circuit that applies erase voltages and manages delays to prevent unwanted programming or erasure of transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If erase voltage is applied to the substrate during erase operation, then memory cells can be erased, but ground and string selection transistors may inadvertently enter quasi-on or turn-on states causing programming or erasure issues
Solution Approach 1:
The patent applies preliminary anti-action by pre-configuring the voltage generating circuit to control the voltages of ground selection lines and string selection lines before the erase operation begins. The circuit is designed to maintain these lines at appropriate voltage levels (e.g., ground voltage or controlled potential) that prevent the selection transistors from entering quasi-on or turn-on states during the subsequent application of erase voltage to the substrate. This preventive voltage control mechanism counteracts the potential harmful effect before it can occur.
Solution Approach 2:
The voltage generating circuit serves as an intermediary component that mediates between the erase voltage source and the selection transistors. It actively manages the voltage distribution across the memory structure, ensuring that while the substrate receives the full erase voltage, the ground and string selection lines are maintained at controlled potentials through this intermediate control layer, thereby preventing unintended transistor state changes.
2Productivity
If voltage difference between substrate and selection lines is not controlled, then erase operation can proceed, but selection transistors may be programmed or erased inadvertently
Solution Approach 1:
The voltage generating circuit implements feedback control by continuously monitoring and adjusting the voltages of ground selection lines and string selection lines based on the substrate voltage level. The circuit responds to changes in substrate potential by modulating the selection line voltages to maintain appropriate voltage differences, ensuring that selection transistors remain in the desired off state throughout the erase operation while allowing the erase process to proceed efficiently.
Solution Approach 2:
The patent applies dynamics by making the voltage control adaptive rather than static. The voltage generating circuit dynamically adjusts the voltages of ground and string selection lines in response to changing conditions during the erase operation, such as varying substrate potential or timing phases. This dynamic control allows the system to maintain precise voltage relationships throughout the entire erase process, preventing unintended transistor state changes while preserving erase speed.
Data Source
AI summary
Provided are erase methods for a memory device which includes a substrate and multiple cell strings provided on the substrate, each cell string including multiple cell transistors stacked in a direction perpendicular to the substrate. The erase method includes applying a ground voltage to a ground selection line connected with ground selection transistors of the cell strings; applying a ground voltage to string selection lines connected with selection transistors of the cell strings; applying a word line erase voltage to word lines connected with memory cells of the cell strings; applying an erase voltage to the substrate; controlling a voltage of the ground selection line in response to applying of the erase voltage; and controlling voltages of the string selection lines in response to the applying of the erase voltage.