Semiconductor Memory Error Correction via Interleaved Parity Storage
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Solution Overview
Problem
The increasing reduction in fabrication design rules of DRAM devices leads to higher bit errors in memory cells, deteriorating the functionality, reliability, and yield of dynamic random access memory (DRAM) devices, which existing technologies have not effectively addressed.
Innovation Solution
A semiconductor memory device is designed with a memory cell array, an error correction circuit, and a control logic circuit that generates and stores parity data using an error correction code (ECC) represented by a generation matrix, interleaving main data and parity data to correct multiple error bits and mis-corrected bits, enhancing error detection and correction capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fabrication design rules are reduced to increase memory density, then memory capacity is improved, but bit error rate increases
Solution Approach 1:
The memory system is segmented into multiple sub-array blocks (k+1 blocks) where main data and parity data are distributed across different segments. This segmentation allows the error correction circuit to identify and correct errors in specific segments without affecting the entire memory array, thereby maintaining reliability while supporting higher density through efficient use of correction codes.
Solution Approach 2:
Parity data is generated and stored in advance along with the main data using ECC codes before errors occur. The control logic circuit pre-arranges the storage of main data in first through k-th sub-array blocks and parity data in (k+1)-th sub-array blocks, enabling proactive error correction rather than reactive handling, thus maintaining reliability as density increases.
2Reliability
If conventional ECC is used to correct errors, then single error bits are corrected, but multiple error bits and mis-corrected bits cannot be corrected
Solution Approach 1:
The invention merges multiple ECC capabilities into a unified system that handles both single error correction and multiple error detection. The error correction circuit combines the benefits of distributed parity storage across (k+1) sub-array blocks with enhanced detection logic that can identify when multiple errors have occurred, preventing mis-correction and thereby improving reliability without proportionally increasing complexity.
Solution Approach 2:
The error correction circuit incorporates feedback mechanisms where the detection of error patterns (including multiple errors and mis-corrected bits) feeds back to the control logic circuit. This feedback enables the system to adjust its correction strategy, such as identifying when parity data from multiple sub-array blocks indicates uncorrectable errors, thereby enhancing the overall error handling capability beyond conventional single-error correction.
3Reliability
If main data and parity data are stored separately in different sub-array blocks, then error detection is improved, but access time increases
Solution Approach 1:
The invention organizes data storage in an additional dimensional structure by distributing main data across first through k-th sub-array blocks and parity data across (k+1)-th sub-array blocks in the second direction. This multi-dimensional arrangement allows parallel access to multiple blocks simultaneously, offsetting the time penalty of distributed storage through concurrent operations, thereby maintaining efficient access times while enhancing error detection capability.
Data Source
AI summary
A semiconductor memory device includes a memory cell array, an error correction circuit, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array is coupled to word-line and bit-lines and is divided into sub array blocks. The error correction circuit generates parity data based on main data using an error correction code (ECC). The control logic circuit controls the error correction circuit and the I/O gating circuit based on a command and address. The control logic circuit stores the main data and the parity data in (k+1) target sub array blocks in the second direction among the sub array blocks, and controls the I/O gating circuit such that a portion of the (k+1) target sub array blocks store both of a portion of the main data and a portion of the parity data.