Memory Device Error Injection Circuit for ECC Logic Isolation
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Solution Overview
Problem
Existing memory devices with Error Code Correction (ECC) logic face difficulties in distinguishing between errors occurring in memory cells and those occurring in the ECC logic itself, making it challenging to accurately analyze errors within the memory device.
Innovation Solution
Incorporating an error injection circuit that allows for the injection of controlled error data into both normal and parity write drivers and sense amplifiers, enabling the simulation and analysis of errors within the memory device, including external, patterned, and random errors, to differentiate between memory cell defects and ECC logic errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Error Code Correction (ECC) logic is used to correct errors in memory devices, then error correction capability is improved, but it becomes difficult to determine whether the error occurred in a memory cell or in the ECC logic itself
Solution Approach 1:
The invention segments the error analysis process by creating separate test modes: one that tests only memory cells and another that tests only the ECC logic. This is achieved by providing separate first and second test data generation circuits that generate different test patterns, allowing independent testing of each component without interference from the other.
Solution Approach 2:
The invention introduces an intermediary testing mechanism using distinct test data generation circuits and control logic that mediates between the memory cell array and ECC logic. The first test data generation circuit generates test data for memory cell testing, while the second generates test data for ECC logic testing, with control logic that directs these tests independently through the same ECC path.
2Measurement precision
If various error testing methods are implemented to identify error sources, then error analysis precision is improved, but device complexity increases
Solution Approach 1:
The invention achieves multi-functionality by using a single shared data path and ECC logic that can operate in multiple modes: normal operation mode, memory cell test mode, and ECC logic test mode. The same physical circuits are reused for different purposes by controlling the data generation and injection mechanisms, avoiding the need for completely separate test circuits.
Solution Approach 2:
The invention implements preliminary action by generating test data in advance through dedicated test data generation circuits before actual testing occurs. The first test data generation circuit prepares test patterns for memory cell testing, and the second prepares test patterns for ECC logic testing, allowing systematic error injection and analysis before real errors occur.
Data Source
AI summary
A memory device includes a normal cell array, a parity cell array, and a plurality of normal write drivers suitable for writing normal write data in the normal cell array. The memory device also includes a plurality of parity write drivers suitable for writing parity write data corresponding to the normal write data, in the parity cell array, and an error injection circuit suitable for injecting error write data to at least one among the plurality of the normal write drivers and the plurality of the parity write drivers to exactly analyze an error of the memory device.