Non-Volatile Memory Error Detection for Internal Data Moves
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Solution Overview
Problem
In non-volatile memory devices, internal data move operations are performed without error detection and correction, leading to potential data integrity issues during memory cell erasing, as existing ECC engines do not engage during these operations.
Innovation Solution
Incorporating an error detecting code (EDC) circuit within the non-volatile memory device that uses parity bits or ECC data to detect and correct errors during internal data moves, allowing the memory controller to read and correct data errors using an error register and ECC operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If internal data move operations are performed without error detection, then device complexity is reduced, but data integrity deteriorates
Solution Approach 1:
The patent applies preliminary action by performing error detection using parity bits before the internal data move operation completes. The parity bit is calculated and stored alongside the data, then used to detect errors during the move operation, allowing error detection to be prepared in advance without adding complex real-time correction mechanisms.
Solution Approach 2:
The patent uses a simple parity bit mechanism rather than complex ECC schemes. The parity bit is a lightweight, disposable error detection mechanism that provides sufficient protection for internal data moves without the overhead of multiple ECC schemes, reducing device complexity while maintaining adequate reliability.
2Reliability
If multiple ECC schemes are implemented, then data integrity is improved, but device complexity and cost increase
Solution Approach 1:
The patent employs a simple parity bit mechanism instead of multiple complex ECC schemes. This disposable, lightweight error detection method provides adequate protection for internal data moves without the computational overhead and complexity of implementing multiple ECC algorithms, thus maintaining reliability while minimizing device complexity.
Solution Approach 2:
The patent extracts the essential error detection function from complex ECC schemes and implements it through a simple parity bit. By taking out only the necessary error detection capability and removing unnecessary complexity, the patent achieves data integrity protection without the burden of multiple ECC implementations.
Data Source
AI summary
Data move operations in a memory device are described that enable identification of data errors. Error detection circuitry in the memory device can be operated using parity data or ECC data stored in the memory. Results of the error detection can be accessed by a memory controller for data repair operations by the controller.