Non-Volatile Memory Error Correction by Bit-Level Voltage Tuning
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Solution Overview
Problem
Non-volatile memory systems face challenges in ensuring reliable data retrieval due to errors in threshold voltage distributions, which can lead to unsuccessful data reading.
Innovation Solution
The system identifies memory cells with error bits in upper and lower tails of threshold voltage distributions and adjusts their threshold voltages to move them closer to the center of their respective distributions using bit-level erase and program operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If data is stored in non-volatile memory, then data retention capability is improved, but reading errors occur due to threshold voltage distribution tails
Solution Approach 1:
The patent applies preliminary action by performing bit-level threshold voltage adjustments on memory cells in the tails of threshold voltage distributions before read operations. The system identifies memory cells with threshold voltages in upper or lower tails and proactively adjusts them to move closer to the center of their respective distributions, preventing reading errors before they occur. This pre-adjustment mechanism resolves the contradiction by maintaining data retention while preemptively eliminating sources of reading errors.
2Reliability
If threshold voltage adjustments are performed on memory cells, then reading reliability is improved, but additional programming operations are required
Solution Approach 1:
The patent applies local quality by performing threshold voltage adjustments only on specific memory cells that have threshold voltages in the tails of distributions, rather than adjusting all memory cells uniformly. The system identifies and targets only those memory cells that exhibit reading errors or are prone to errors, applying adjustments locally to these problematic cells. This selective approach improves reading reliability while minimizing the scope and complexity of additional programming operations required.
3Reliability
If bit-level erase and program operations are used to adjust threshold voltages, then error correction capability is improved, but processing time increases
Solution Approach 1:
The patent applies partial action by performing bit-level erase and program operations only on the subset of memory cells that have threshold voltages in the tails of distributions and are causing reading errors. Rather than re-programming or adjusting all memory cells in a block, the system identifies and processes only the problematic portion (the tails), which represents a fraction of the total memory cells. This partial adjustment approach improves error correction capability while significantly reducing the processing time compared to comprehensive re-programming.
Data Source
AI summary
In response to determining that a data set was not read successfully, the system identifies memory cells storing error bits that are in upper tails and lower tails of the threshold voltages distributions. To reduce the number of errors, memory cells storing error bits that are in upper tails have their threshold voltages reduced by bit level erase and memory cells storing error bits that are in lower tails have their threshold voltages increased by bit level program. The identification of which memory cells with error bits are in upper tails and lower tails can be determined on the memory die using a series of latch based operations.