Memory Extensible Chip Substrate Network Bandwidth
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Solution Overview
Problem
Integrating multiple memory modules on a chip while maintaining high memory bandwidth and reducing access latency is a challenge, as direct connections limit bandwidth and increase average hop count, leading to decreased processing rates.
Innovation Solution
A memory extensible chip design that integrates multiple memory module sets on a substrate with a substrate network, allowing the processor to communicate through different interfaces and bypass heavy-loaded paths, and dynamically select communication paths based on hop count and latency to balance load and reduce access latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory modules are directly connected to the processor, then memory capacity is increased, but bandwidth per memory module decreases to 1/N of total bandwidth
Solution Approach 1:
The memory system is segmented into multiple memory module sets, each set connected to the processor through dedicated communication interfaces. This segmentation allows different memory sets to operate independently with guaranteed bandwidth, resolving the bandwidth dilution problem when multiple memory modules are connected.
Solution Approach 2:
A substrate network is introduced as an intermediary communication channel between memory modules within the same set. This substrate network provides additional communication paths that bypass the processor, enabling memory modules to exchange data directly and effectively increasing the usable bandwidth for each memory module.
2Quantity of substance
If multiple memory modules are connected through the processor, then memory capacity is increased, but average hop count increases and access rate decreases
Solution Approach 1:
Memory modules are organized into separate sets with dedicated interfaces, creating multiple independent access paths to the processor. This segmentation reduces the average hop count by providing direct access routes, preventing all memory access traffic from funneled through a single bottleneck path.
Solution Approach 2:
The substrate network adds a new dimensional communication path within the substrate, allowing memory modules to communicate laterally without ascending through the processor hierarchy. This dimensional change creates shortcuts that reduce access latency while maintaining expanded memory capacity.
Data Source
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Figure 3
AI summary
A memory extensible chip (200) is provided. The chip (200) includes a substrate (240), and a processor (230), a first memory module set (210), and a second memory module set (220) that are integrated on the substrate (240), where the processor (230) communicates with at least one memory module in the first memory module set (210) by using a first communications interface (250), and the processor (230) communicates with at least one memory module in the second memory module set (220) by using a second communications interface (260); and a memory module in the first memory module set (210) communicates with a memory module in the second memory module set (220) by using a substrate network, where the substrate network is a communications network located inside the substrate (240). In this way, the processor (230) can access a memory module in the first memory module set (210) by using the second memory module set (220), so that high memory bandwidth can be ensured while a latency of accessing the memory module by the processor (230) is shortened.