Memory Fabrication Using Preliminary Gate Dielectric Formation
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Solution Overview
Problem
In semiconductor device fabrication, the miniaturization of memory devices leads to a short channel effect due to reduced line widths, causing threshold voltage reduction and increased sub-threshold current, and high thermal budget processes compromise the size and quality of buried diffusion regions and inter-gate dielectric layers.
Innovation Solution
A method is developed where the gate dielectric film is formed in the periphery area before the buried diffusion region, preventing expansion and maintaining the size of the buried diffusion region, and the inter-gate dielectric layer is protected by forming it after the conductive layer, ensuring its quality and properties are preserved.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If thermal processes are performed to form gate insulating layers for high voltage devices, then the gate insulating layers are formed, but the buried diffusion region expands
Solution Approach 1:
The gate dielectric film is formed in the periphery area before forming the buried diffusion region in the memory array area. This preliminary action ensures that subsequent thermal processes for forming thick gate insulating layers in high voltage regions will not affect the already-formed buried diffusion region, preventing its expansion and maintaining manufacturing precision.
2Productivity
If miniaturization is pursued to increase integration, then device density increases, but short channel effect worsens
Solution Approach 1:
The patent applies different gate dielectric film thicknesses in different regions: a first thickness in the high voltage transistor region and a second thickness in the low voltage transistor region. This local differentiation allows optimized electrical characteristics for each region while maintaining overall device integration and minimizing short channel effects through precise local control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes the short channel effect and improves device characteristics by maintaining the size of the buried diffusion region and preserving the inter-gate dielectric layer quality, enhancing the overall performance and reliability of the memory device.
Implementation Method 1
The gate dielectric film is formed by performing thermal processes, for example
Implementation Method 2
The buried diffusion lines, which constitute either source lines or drain lines, are formed by implanting dopants in the substrate
Data Source
AI summary
A method for fabrication a memory having a memory area and a periphery area is provided. The method includes forming a gate insulating layer over a substrate in the periphery area. Thereafter, a first conductive layer is formed in the memory area, followed by forming a buried diffusion region in the substrate adjacent to the sides of the first conductive layer. An inter-gate dielectric layer is then formed over the first conductive layer followed by forming a second conductive layer over the inter-gate dielectric layer. A transistor gate is subsequently formed over the gate insulating layer in the periphery area.