Semiconductor Memory Fail Bit Search via Daisy Chain Logic
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Solution Overview
Problem
In NAND flash memory devices, accurately writing data into all memory cells in a single operation is challenging, requiring a three-step write sequence involving writing, verifying, and searching for fail bits, which complicates the data write process and slows down the write speed.
Innovation Solution
A semiconductor memory device configuration that includes memory cells connected via a data bus with holding circuits for fail information, daisy chain circuits to shift logical sums of fail information, and a search circuit to identify fail bits, allowing for efficient fail bit detection and count accumulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a three-step write sequence (writing, verifying, searching for fail bits) is used to ensure accurate data writing, then data write reliability is improved, but data write speed deteriorates
Solution Approach 1:
The patent applies preliminary action by performing fail bit search and counting operations during the verification stage rather than as a separate subsequent step. The search circuit identifies fail bits and the count circuit accumulates fail bit counts concurrently with the writing and verification operations, eliminating the need for a separate search phase and thereby improving write speed while maintaining reliability.
2Reliability
If fail bit search and counting operations are performed sequentially after writing and verification, then data write reliability is ensured, but the time required for program stages increases
Solution Approach 1:
The patent merges the fail bit search function and fail bit counting function into a single integrated operation that occurs during the verification stage. The search circuit and count circuit work concurrently, combining what were previously separate sequential operations into one unified process, thereby reducing the total time required for program stages while ensuring data write reliability.
Solution Approach 2:
The patent implements continuity of useful action by performing fail bit search and counting operations during the verification stage rather than waiting for it to complete. The search circuit continuously identifies fail bits and the count circuit continuously accumulates counts throughout the verification process, making the verification stage serve dual purposes and eliminating idle time between operations.
3Productivity
If a circuit is added to count the number of fail bits to enable faster write operations, then data write speed is improved, but device complexity increases
Solution Approach 1:
The patent applies multi-functionality by designing the verification circuit to serve multiple purposes: it performs data verification, fail bit search, and fail bit counting simultaneously. The same circuit resources used for verification are also utilized for identifying and counting fail bits, eliminating the need for separate dedicated circuits and thereby improving write speed without proportionally increasing device complexity.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes units each including memory cells, a data bus connected to each of the units and having data lines, holding circuits configured to hold fail information supplied from the unit through the data bus as a verify result after writing data, and provided in association with the data lines, respectively, daisy chain circuits configured to shift a flag includes a logical sum of the fail information held in the holding circuits, and provided in association with the data lines, respectively, and a search circuit configured to search for fail bits in the units based on the flag.