Memory Cell Parameter Control Using Fail Bit Detection Time
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Solution Overview
Problem
Memory devices experience reliability issues due to retention, which causes deterioration of memory cells, affecting read, program, and erase operations, necessitating improved reliability through optimization based on deterioration degrees.
Innovation Solution
A memory device with a peripheral circuit for fail bit detection and control logic to set target parameters based on comparison between fail bit detection time and reference time, optimizing main operations like read, program, and erase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory operations are performed without considering retention deterioration, then operation speed is maintained, but reliability of read, program, and erase operations decreases
Solution Approach 1:
The patent applies preliminary action by performing a fail bit detection operation before the main memory operation to measure the deterioration degree of memory cells. Based on this pre-measurement, target parameters are determined in advance to compensate for retention effects, ensuring reliable operations without adding complex real-time control mechanisms during the main operation.
Solution Approach 2:
The memory device performs self-diagnosis through the fail bit detection operation, automatically measuring its own deterioration degree and adjusting its operation parameters accordingly. This self-service mechanism eliminates the need for external complex control systems while improving operational reliability based on the device's actual state.
2Measurement precision
If fail bit detection operation is performed on all memory cells, then deterioration degree is accurately determined, but operation time increases
Solution Approach 1:
The patent applies local quality by selectively performing fail bit detection on specific memory cells that are more susceptible to retention effects, such as cells at particular positions in the array or cells that have been frequently accessed. This selective approach maintains measurement accuracy for critical cells while reducing the overall time compared to checking all memory cells.
Solution Approach 2:
The patent performs partial action by conducting fail bit detection on a subset of memory cells rather than all cells. The detection targets memory cells with higher deterioration risk based on their position, access history, or other characteristics, achieving sufficient measurement precision for reliable operation without the time cost of comprehensive detection.
3Reliability
If target parameters are adjusted based on deterioration degree, then operation reliability improves, but control complexity increases
Solution Approach 1:
The patent applies parameter changes by adjusting target parameters such as read voltage, program voltage, erase voltage, or operation timing based on the measured deterioration degree from fail bit detection. These parameter adjustments compensate for retention effects and improve operation reliability without requiring complex control logic, as the changes follow predetermined relationships between deterioration level and optimal parameters.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances memory operation reliability by adapting parameters to the deterioration degree of memory cells, improving the performance and longevity of the device.
Implementation Method 1
sensing a cell current of the selected memory cell to detect a time until the cell current exceeds a reference current
Data Source
AI summary
The present technology relates to an electronic device. According to the present technology, a memory device may include a plurality of memory cells, a peripheral circuit, and a control logic. The peripheral circuit may perform a fail bit detection operation on memory cells selected from among the plurality of memory cells. The control logic may control the peripheral circuit to set target parameters related to a main operation based on a comparison result between a fail bit detection time measured in the fail bit detection operation and a reference time, and perform the main operation on the selected memory cells based on the target parameters.