Memory Failure Analysis Using Coordinate-Based MOD Classification

The patent segments the memory array into multiple regions based on layout design characteristics (e.g., different cell types, word line/bit line intersections, contact regions). Each region is assigned specific coordinates that reflect its structural features. This segmentation enables targeted analysis of different failure modes in different regions, improving classification precision while reducing the need for exhaustive analysis of the entire array.

The patent performs preliminary classification of failure coordinates based on their spatial relationships with design and layout features before detailed failure analysis. By pre-categorizing coordinates according to their location in the memory array (e.g., near contacts, in specific cell regions, at word line intersections), the system prepares structured data that accelerates subsequent root cause determination, reducing overall analysis time.

The patent introduces coordinate-based spatial classification as an intermediary step between raw failure data and root cause determination. By mapping failure coordinates to specific design and layout features (e.g., identifying that failures occur at word line/bit line intersections or near contact regions), the system creates structured intermediate information that bridges the gap between basic failure detection and detailed cause analysis, enabling faster root cause identification.

The patent replaces the traditional mechanical/manual failure analysis process with an automated coordinate-based classification system. Instead of manually examining each failure and tracing it through design documents, the system automatically processes failure coordinates, compares them with layout data, and identifies patterns associated with specific failure modes (e.g., contact opens, line shorts, cell defects), significantly reducing analysis time while maintaining accuracy.