Memory Finger Insulation Structure to Prevent Layer Exposure
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor memory devices face challenges in manufacturing due to the lack of effective insulation layers that prevent the exposure of semiconductor layers and gate insulating films during processing, leading to potential short circuits and increased contact resistance.
Innovation Solution
The implementation of nitrogen (N) and silicon (Si) containing insulating layers, specifically silicon nitride (SiN) and silicon oxynitride (SiON), between conductive layers and semiconductor layers, along with a high-dielectric-constant insulating layer, to create a structured insulation that protects the semiconductor layers and maintains the integrity of the device during manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional insulating layers are used without nitrogen and silicon containing materials, then the device structure is simpler, but the semiconductor layers and gate insulating films are exposed during processing causing short circuits and increased contact resistance
Solution Approach 1:
The insulating layer is divided into multiple segments: a first insulating layer containing nitrogen and silicon (silicon nitride or silicon oxynitride) and a second insulating layer. This segmentation allows each layer to perform specific functions - the first layer prevents exposure and short circuits, while the second layer provides additional insulation, thereby resolving the contradiction between reliability and structural simplicity.
Solution Approach 2:
The patent uses composite insulating layer structures combining different materials - specifically silicon nitride (SiN) or silicon oxynitride (SiON) in the first layer, and other insulating materials in the second layer. This composite approach provides both the chemical stability needed to prevent exposure and the electrical insulation required, addressing the reliability-complexity tradeoff.
2Manufacturing precision
If no nitrogen and silicon containing insulating layers are used, then the manufacturing process is simpler, but contact resistance increases due to exposure of semiconductor layers
Solution Approach 1:
The nitrogen and silicon containing insulating layer is formed preliminarily before subsequent processing steps that could expose the semiconductor layers. This preliminary action of creating a protective barrier early in the manufacturing process prevents contact resistance issues without requiring complex post-processing corrections, thus balancing manufacturing precision with ease of manufacture.
3Reliability
If protective insulating layers are added to prevent exposure, then short circuit risk is reduced, but the number of layers and processing steps increases
Solution Approach 1:
The patent combines the protective function and insulating function into a single integrated insulating layer structure containing nitrogen and silicon. This merging of functions eliminates the need for separate protective and insulating layers, maintaining short circuit prevention while reducing the total number of layers and processing steps, thereby preserving manufacturing efficiency.
Data Source
AI summary
A semiconductor memory device includes finger structures arranged in a first direction, a bit line disposed on one side in a stacking direction with respect to the finger structures, and an inter-finger insulating layer disposed between two finger structures. A first finger structure includes conductive layers, a semiconductor layer opposed to the conductive layers, a first insulating layer disposed between the bit line and the conductive layers, and a second insulating layer disposed between the first insulating layer and the conductive layers. A distance between the first insulating layer and the inter-finger insulating layer at a position corresponding to a surface on a side of the bit line of the first insulating layer is larger than a distance between the second insulating layer and the inter-finger insulating layer at a position corresponding to a surface on an opposite side of the bit line of the second insulating layer.