Semiconductor Memory Flag Cell Erase Control
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Solution Overview
Problem
The reliability of semiconductor memory devices, such as flash memory, deteriorates over time due to increasing program/erase cycles, leading to a rise in threshold voltage without data change, which affects their performance and longevity.
Innovation Solution
Incorporating a memory cell array with flag cells to indicate data storage status, allowing a peripheral circuit to selectively omit or perform erase operations based on the flag cell data, and using a soft erase pulse when appropriate, to reduce memory cell deterioration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If erase operations are performed frequently to maintain data integrity, then data reliability is improved, but memory cell deterioration increases
Solution Approach 1:
The patent performs preliminary verification by reading flag cells before executing erase operations. This preliminary action identifies which memory blocks actually contain data requiring erasure, preventing unnecessary erase operations and reducing memory cell deterioration while maintaining data reliability.
Solution Approach 2:
The patent implements a feedback mechanism where flag cell data is read and analyzed to determine whether erase operations are necessary. This feedback loop allows the system to make informed decisions about erase operations, balancing data integrity maintenance with memory cell preservation.
2Manufacturing precision
If verify operations are performed repeatedly to ensure complete erasure, then erase completeness is improved, but operational time increases
Solution Approach 1:
The patent performs preliminary reading of flag cells before erase operations to identify which blocks need erasure. This preliminary action enables targeted erasing and verification, reducing the number of repeated verify operations needed while ensuring complete erasure of only necessary blocks.
Solution Approach 2:
The patent applies erase operations selectively based on flag cell status rather than performing excessive erasures on all blocks. This partial action approach verifies and erases only the necessary portions, reducing operational time while maintaining erase completeness.
Data Source
AI summary
A semiconductor memory device comprises a memory cell array including a plurality of memory blocks each including a plurality of pages, wherein each of the plurality of pages includes at least one flag cell indicating whether data is in a corresponding page, and a peripheral circuit configured to read data of flag cells of a selected memory block in response to an erase request and to omit an erase operation on the selected memory block based on the data of the flag cells.