Nonvolatile Memory Floating Gate Protrusions for Coupling Ratio
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Solution Overview
Problem
In nonvolatile memory devices, particularly EEPROM devices, reducing the thickness of the inter-gate dielectric layer to enhance integration density is limited by increased leakage current, which degrades program and erasure efficiency.
Innovation Solution
The method involves forming a molding pattern on a semiconductor substrate with a conductive pattern that includes a body plate and protrusions extending from the body plate, increasing the overlap area between the floating gate and the control gate, thereby enhancing the coupling ratio without degrading integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the thickness of the inter-gate dielectric layer is reduced to enhance integration density, then integration density is improved, but leakage current increases degrading program and erasure efficiency
Solution Approach 1:
The patent extends the floating gate structure vertically by forming protrusions that penetrate through the inter-gate dielectric layer to contact the control gate. This three-dimensional configuration increases the overlap area between floating gate and control gate without reducing the inter-gate dielectric layer thickness, thereby maintaining electrical insulation while improving coupling ratio and program/erasure efficiency.
Solution Approach 2:
The protrusions of the floating gate are nested within the inter-gate dielectric layer structure, extending from the floating gate through the dielectric to contact the control gate. This nested configuration allows the floating gate to effectively interact with the control gate while being contained within the established dielectric layer boundaries.
2Reliability
If the overlap area between control gate and floating gate is increased to improve coupling ratio, then program and erasure efficiency are improved, but device area increases reducing integration density
Solution Approach 1:
Instead of increasing the planar overlap area between control gate and floating gate, the patent utilizes the vertical dimension by forming protrusions that extend through the inter-gate dielectric layer. This increases the effective coupling area in the vertical direction while maintaining compact planar dimensions, thus improving program/erasure efficiency without sacrificing integration density.
Solution Approach 2:
The protrusions are formed at specific locations (edges or corners) of the floating gate structure, concentrating the coupling enhancement in localized regions. This allows the coupling ratio to be improved without requiring a proportional increase in the overall device area, as the enhanced coupling is achieved through targeted three-dimensional structuring rather than uniform planar expansion.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases the coupling ratio, improving program and erasure efficiency while maintaining high integration density by maximizing the overlap area between the floating gate and the control gate within a limited planar area.
Implementation Method 1
When a program voltage or an erasure voltage is applied between the control gate and the floating junction region, a Fowler-Nordheim (F-N) tunneling current may flow through the tunnel oxide layer.
Implementation Method 2
The memory transistor may include a floating gate which is electrically insulated from other conductive elements adjacent thereto.
Data Source
AI summary
A method of manufacturing a nonvolatile memory device is provided. The method includes forming an isolation layer in a semiconductor substrate defining an active region and forming a molding pattern on the isolation layer. A first conductive layer is formed on a sidewall and a top surface of the molding pattern and on the semiconductor substrate. The first conductive layer on the top surface of the molding pattern is selectively removed forming a conductive pattern. The conductive pattern includes a body plate disposed on the active region and a protrusion which extends from an edge of the body plate onto the sidewall of the molding pattern. The molding pattern is then removed. An inter-gate dielectric layer is formed on the isolation layer and the conductive pattern. Nonvolatile memory devices manufactured using the method are also provided.