Memory Structure With Varying Floating Gate Widths
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Solution Overview
Problem
Current non-volatile memory devices face challenges in enhancing electrical performance, program efficiency, and read accuracy due to limitations in transistor design and voltage application methods.
Innovation Solution
The memory structure incorporates specific transistor configurations, including select and floating gate transistors with varying gate widths and lengths, and employs ramp and auxiliary voltages in programming and reading methods to optimize current usage and reduce errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gate width of floating gate transistors is increased to improve program efficiency, then program performance is improved, but device area and complexity increase
Solution Approach 1:
The memory array is divided into multiple blocks with different floating gate transistor configurations. First block uses a first transistor type with specific gate width, while second block uses a second transistor type with different gate width. This segmentation allows each block to be optimized for different program efficiency requirements without increasing overall device complexity.
Solution Approach 2:
Different regions of the memory device use different transistor designs tailored to local performance requirements. The first block employs transistors with one gate width configuration optimized for high program efficiency, while the second block uses transistors with another gate width configuration optimized for different performance characteristics. This local quality approach resolves the contradiction by allowing program efficiency optimization in specific regions without requiring all transistors to be complex.
2Productivity
If ramp voltage is applied to improve program efficiency, then programming speed is improved, but power consumption increases
Solution Approach 1:
Ramp voltage is applied in a time-dependent manner during the programming operation rather than as a constant voltage. The voltage increases gradually over time following a ramp profile, which allows controlled charge injection into the floating gate. This periodic action achieves fast programming speed while managing peak power consumption by spreading the energy delivery over time.
3Measurement precision
If auxiliary voltage is applied during reading to prevent reading errors, then reading accuracy is improved, but power consumption increases
Solution Approach 1:
An auxiliary voltage is applied to the control gate during read operations to facilitate accurate sensing of the stored data state. This intermediary voltage helps overcome threshold variations and ensures reliable reading by creating a sufficient voltage differential for sense amplification. The auxiliary voltage is applied only during the brief read window, minimizing overall power consumption while achieving high reading accuracy.
4Reliability
If non-volatile memory is used to retain data after power off, then data retention is improved, but electrical performance deteriorates
Solution Approach 1:
The memory device is segmented into multiple blocks with different transistor configurations optimized for different operational characteristics. This segmentation allows the system to leverage the data retention advantage of non-volatile memory while compensating for electrical performance limitations through architectural diversity and selective block usage.
Solution Approach 2:
Different blocks use transistors with different gate widths and configurations, creating parameter variations that optimize electrical performance. By changing physical parameters such as gate width across different blocks, the device achieves improved current drive and switching characteristics while maintaining the non-volatile data retention property.
Data Source
AI summary
A memory structure including a first select transistor, a first floating gate transistor, a second select transistor, a second floating gate transistor, and a seventh doped region is provided. The first select transistor includes a select gate, a first doped region, and a second doped region. The first floating gate transistor includes a floating gate, the second doped region, and a third doped region. The second select transistor includes the select gate, a fourth doped region, and a fifth doped region. The second floating gate transistor includes the floating gate, the fifth doped region, and a sixth doped region. A gate width of the floating gate in the second floating gate transistor is greater than a gate width of the floating gate in the first floating gate transistor. The floating gate covers at least a portion of the seventh doped region.