Memory Fuse Read Sequencing for Noisy Power-On States
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Solution Overview
Problem
Power-on fuse read operations in memory devices can fail due to varying power-up slew rates and power noise, making it difficult to determine if the operation has succeeded or if the fuse data is incorrect.
Innovation Solution
A power-on reading method that generates a power-on signal based on the voltage level, sequentially detects the ready states of multiple circuits, reads fuse states, and uses a shift register circuit with registers triggered by specific logic values to generate a read pass indication signal, ensuring the chip status is accurately determined.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power-on fuse read operation is performed in memory device, then fuse data can be obtained, but operation may fail due to power noise and varying slew rate making it difficult to detect failure
Solution Approach 1:
The patent applies preliminary action by performing the fuse read operation during the power-on sequence before the memory device is fully operational. The read operation is initiated automatically when power voltage reaches a threshold level, capturing fuse data at the earliest possible moment when the device state is known and controlled. This preliminary timing ensures that the read operation completes before power noise and voltage variations occur during subsequent device initialization.
Solution Approach 2:
The patent introduces an intermediary mechanism in the form of a dedicated read status register that captures and holds the result of the fuse read operation. This register acts as a mediator between the fuse read circuit and the rest of the memory device, storing the read status (success or failure) in a stable, queryable location. The status register decouples the transient read operation from the ongoing device operation, allowing reliable status detection independent of subsequent power variations.
2Measurement precision
If sequential detection of multiple circuits and fuse states is performed, then accurate chip status can be determined, but operation time and complexity increase
Solution Approach 1:
The patent segments the chip status detection into distinct, independent stages: power-on signal generation, ready state detection for each circuit, fuse state reading, and status register updating. Each segment is handled by dedicated circuitry that operates independently and sequentially. This segmentation allows each detection task to be optimized separately and completes in a predetermined time window, preventing cascading delays while maintaining comprehensive status checking.
Solution Approach 2:
The patent implements periodic action through clocked register stages that advance through the detection sequence at fixed time intervals. Each ready state detection and fuse read operation is synchronized to a clock cycle, creating a periodic progression through the status detection pipeline. This periodic timing ensures that each detection step completes within a known time frame, and the entire sequence finishes predictably, balancing thoroughness with speed.
Data Source
AI summary
A power-on reading method of a memory device includes: generating a power-on signal according to a voltage level of a power voltage of the memory device; respectively detecting a plurality of ready states of a plurality of circuits in the memory device sequentially to generate a plurality of ready signals; reading a plurality of fuse states sequentially to generate a plurality of fuse state signals; and shifting a reference signal sequentially to generate a read pass indication signal according to the power-on signal, the plurality of ready signals and the plurality of fuse state signals by a plurality of registers coupled in series, wherein each of the plurality of registers is triggered when the power-on signal, corresponding ready signal or corresponding fuse state signal is at a setting logic value.