3D Memory Gate Stack Barrier Layout for Contact Isolation
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Solution Overview
Problem
As integration density of semiconductor devices increases, electrical characteristics and production yield deteriorate, necessitating improvements in semiconductor device design to enhance performance and reliability.
Innovation Solution
A semiconductor device design featuring alternately stacked first and second gate stacks with insulating and conductive patterns, a memory channel structure, penetration contact, and a barrier pattern on either side of the penetration contact, which includes connection insulating patterns and a barrier pattern between the gate stacks to protect and position the penetration contact effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If integration density of semiconductor devices is increased, then productivity and functionality are improved, but electrical characteristics and production yield deteriorate
Solution Approach 1:
The device is divided into multiple gate stacks (first gate stack and second gate stack) with alternating insulating and conductive patterns. This segmentation allows for better electrical isolation and reduced interference between adjacent structures, improving electrical characteristics while maintaining high integration density.
Solution Approach 2:
Connection insulating patterns are introduced as intermediary elements between the penetration contact and conductive patterns. These insulating patterns act as mediators to prevent direct electrical contact where it is not desired, thereby improving electrical characteristics and production yield while allowing the penetration contact to maintain its positioning function.
2Productivity
If thickness of connection insulating patterns is reduced, then integration density is improved, but electrical isolation may be compromised
Solution Approach 1:
The connection insulating pattern is segmented into multiple discrete insulating regions rather than a continuous thick layer. This segmentation allows for reduced overall thickness while maintaining electrical isolation at critical interfaces, particularly between the penetration contact and conductive patterns.
Solution Approach 2:
The connection insulating patterns are strategically positioned only where electrical isolation is critically needed - specifically between the penetration contact and conductive patterns. This local quality approach allows for minimal thickness elsewhere in the structure, improving integration density while maintaining electrical isolation where it matters most.
3Reliability
If distance between penetration contact and conductive patterns is increased, then electrical characteristics are improved, but device area increases
Solution Approach 1:
Connection insulating patterns are introduced as intermediary elements between the penetration contact and conductive patterns. These insulating patterns enable closer spacing between the penetration contact and conductive patterns while maintaining adequate electrical isolation, thus improving electrical characteristics without increasing device area.
Solution Approach 2:
Instead of increasing horizontal distance to improve electrical characteristics, the design uses vertical stacking with alternating insulating and conductive patterns in the gate stacks. This dimensional change allows for better electrical isolation through the vertical dimension while maintaining compact horizontal footprint.
Data Source
AI summary
A semiconductor device including: a first gate stack including first insulating patterns and first conductive patterns; a second gate stack on the first gate stack, the second gate stack including second insulating patterns and second conductive patterns; a memory channel structure penetrating the first and second gate stacks; a penetration contact penetrating the first and second gate stacks; and a barrier pattern on opposite sides of the penetration contact, the first insulating patterns include a first connection insulating pattern, which is an uppermost one of the first insulating patterns, the second insulating patterns include a second connection insulating pattern which is in contact with a top surface of the first connection insulating pattern, a bottom surface of the barrier pattern is in contact with the top surface of the first connection insulating pattern, and a top surface of the barrier pattern is in contact with the second connection insulating pattern.