Non-Volatile Memory Gate Stack for Coplanar ILD and Lower Resistance
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing contact resistance and minimizing the number of lithography operations while manufacturing semiconductor devices with non-volatile memory cells and peripheral logic circuits, particularly due to height differences in interlayer dielectric layers between these areas, which affect chemical mechanical polishing and increase manufacturing complexity.
Innovation Solution
A method is introduced where a substrate is etched to create a step between non-volatile memory cell and peripheral logic circuit areas before forming interlayer dielectric layers, allowing for the formation of isolation layers and subsequent dielectric and polysilicon layers, and using metal conductive materials for control gates and gates in the non-volatile memory cells to reduce resistance, while minimizing the number of lithography operations by synchronizing gate replacement processes across both areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a substrate is etched to create a step between non-volatile memory cell and peripheral logic circuit areas, then height differences in interlayer dielectric layers are reduced, but the manufacturing process complexity increases
Solution Approach 1:
The substrate is etched to create a step structure before forming the interlayer dielectric layers. This preliminary action establishes height differences in the substrate that compensate for subsequent dielectric layer thickness variations, ensuring that the top surfaces of the interlayer dielectric layers become substantially coplanar across different circuit areas.
2Reliability
If metal conductive materials are used for control gates and gates in non-volatile memory cells, then contact resistance is reduced, but the number of lithography operations increases
Solution Approach 1:
The gate replacement processes for both the non-volatile memory cell area and the peripheral logic circuit area are synchronized and performed simultaneously in a single lithography operation. This merging of operations reduces the total number of lithography steps required while implementing metal gates in both areas, thereby reducing contact resistance without proportionally increasing manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces contact resistance and minimizes the increase in lithography operations by creating a uniform structure and using metal gates in non-volatile memory cells, thereby improving manufacturing efficiency and performance.
Implementation Method 1
a substrate is etched to create a step between non-volatile memory cell and peripheral logic circuit areas
Implementation Method 2
using metal conductive materials for control gates and gates in the non-volatile memory cells to reduce resistance
Data Source
AI summary
A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate and a second dielectric layer disposed between the floating gate and the control gate. The second dielectric layer includes one of a silicon oxide layer, a silicon nitride layer and a multi-layer thereof. The first dielectric layer includes a first-first dielectric layer formed on the substrate and a second-first dielectric layer formed on the first-first dielectric layer. The second-first dielectric layer includes a dielectric material having a dielectric constant higher than silicon nitride.