Memory Gate Driver Circuitry for Flash Cell Voltage Control
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Solution Overview
Problem
In eCT flash memory devices, operating a memory cell in various modes can disturb other non-active cells, and there is a need for concurrent voltage signals to maintain non-active cells in an idle state without increasing the memory array's size.
Innovation Solution
The use of high-voltage and low-voltage driver circuitry to independently drive memory gate and select gate terminals of different memory cells, allowing for concurrent operation modes like read, program, erase, and verify while minimizing area penalty.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional single-voltage memory operation is used, then the memory array size can be kept small, but non-active cells are disturbed during active cell operations
Solution Approach 1:
The patent segments the memory gate voltage control into multiple independent voltage levels (first voltage for non-active cells, second voltage for active cells). This segmentation allows different voltage signals to be applied to different portions of the memory array simultaneously, preventing disturbance to non-active cells while maintaining small array size without requiring additional physical space for control circuitry.
Solution Approach 2:
The patent implements dynamic voltage control where the memory gate driver circuitry can switch between different voltage levels (first voltage level and second voltage level) based on operational mode. This dynamic capability allows the system to adapt voltage signals in real-time, enabling concurrent read, program, erase, and verify operations without increasing memory array area.
2Reliability
If concurrent voltage signals are applied to maintain non-active cells in idle state, then non-active cells remain undisturbed, but device complexity increases
Solution Approach 1:
The memory gate driver circuitry is designed with multi-functionality to generate multiple voltage levels (first voltage and second voltage) using a unified control structure. This universal driver can operate in different modes (read, program, erase, verify) while maintaining non-active cells in idle state, reducing the need for separate dedicated circuits for each function and thereby limiting complexity increase.
Solution Approach 2:
The driver circuitry generates the required multiple voltage signals through internal voltage division and control logic rather than requiring external voltage sources. The circuit self-manages the generation of first and second voltage levels, reducing external complexity while maintaining reliable idle state for non-active cells during concurrent operations.
3Adaptability or versatility
If high-voltage driver circuitry is added to enable concurrent operations, then multi-mode operation is achieved, but area overhead increases
Solution Approach 1:
The patent merges the high-voltage driver functionality with the existing memory gate driver circuitry. By combining the voltage generation and control functions into a single integrated driver structure, the patent achieves concurrent read, program, erase, and verify operations without requiring separate dedicated high-voltage driver circuits, thereby minimizing area overhead in the memory array.
Solution Approach 2:
The patent achieves multi-mode operation by changing voltage parameters (first voltage level and second voltage level) rather than adding separate physical circuits for each operation mode. This parameter-based control allows concurrent operations with minimal additional area, as the same driver circuitry can output different voltage combinations depending on the operational mode required.
Data Source
AI summary
A memory array including a first memory cell including a first memory gate coupled to receive a first signal. The memory array including a second memory cell including a first memory gate coupled to receive a second signal. The magnitude of the second signal is different than the magnitude of the first signal. The memory array including a third memory cell including a first memory gate coupled to receive a third signal. The magnitude of the third signal is different than the magnitude of the first signal and the magnitude of the second signal. The first signal, the second signal and the third signal are received concurrently.