Memory Device Gate-Resistance Storage for Low-Current Read Margin
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Solution Overview
Problem
Existing memory technologies face issues such as large area requirements, high operation current, small read margin, reliability problems, and charge loss, particularly in advanced-OTP memory devices beyond the 28 nanometer technology node, necessitating improved solutions.
Innovation Solution
A memory device comprising a first storage transistor and a first select transistor, where the select transistor changes the resistance of the storage transistor's gate to write data bits, utilizing a cascade connection to reduce the number of elements and area, with the select transistor controlling multiple storage transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional fuse-type wire memory is used, then data storage is achieved, but large area and high operation current are required
Solution Approach 1:
The patent merges the select transistor and storage transistor into a cascade-connected structure where the select transistor's drain connects to the storage transistor's gate. This integration allows the select transistor to control multiple storage transistors sharing common word lines, reducing the total element count while maintaining data storage functionality with lower current requirements
Solution Approach 2:
The select transistor serves multiple functions: it acts as both a control element for selecting storage transistors and as part of the writing mechanism. By controlling the word line signals to multiple storage transistors simultaneously, the select transistor reduces the need for separate control elements, thereby reducing overall device area and element count
2Measurement precision
If traditional fuse-type wire memory is used, then data storage is achieved, but read margin is small
Solution Approach 1:
The patent utilizes resistance changes in the gate dielectric layer of storage transistors during writing operations. By applying high voltage pulses that cause hard-breakdown, the gate resistance changes from high to low state, creating distinct resistance levels that provide a large read margin for data detection without requiring complex additional structures
3Length of moving object
If gate dielectric layer thickness is reduced, then scaling is achieved, but hard-breakdown and reliability problems occur
Solution Approach 1:
The patent applies preliminary high voltage pulses to the gate dielectric layer before normal operation. These preliminary action pulses induce controlled hard-breakdown that creates stable low-resistance states, preparing the gate for reliable subsequent operations while managing the reliability risks of thin dielectric layers through controlled stress application
4Quantity of substance
If charge storage mechanism is used, then data storage is achieved, but charge loss problem occurs
Solution Approach 1:
The patent replaces traditional charge storage mechanisms (such as floating gates or SONOS) with a resistance-based storage approach. By using gate dielectric layer resistance changes rather than charge accumulation, the system avoids charge loss problems while maintaining data storage capability through distinct resistance states that can be reliably detected
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution allows for efficient data storage with reduced element count and area, enabling reliable operation with low current consumption and improved read margin by changing the resistance of the storage transistor's gate to represent logic values 0 and 1.
Implementation Method 1
The first select transistor is configured to change the resistance of a gate of the first storage transistor, to write the first data bit into the first storage transistor
Data Source
AI summary
A memory device includes a first storage transistor and a first select transistor. The first storage transistor is configured to store a first data bit. The first select transistor is configured to change the resistance of a gate of the first storage transistor, to write the first data bit into the first storage transistor, a first terminal of the first select transistor being coupled to the gate of the first storage transistor. A method of operating a memory device is also disclosed herein.