Nonvolatile Memory Gate Segmentation for Short Channel Effect
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Solution Overview
Problem
Non-volatile memory devices face challenges such as the 'short channel effect' and trap-assisted leakage current, which affect device performance and reliability, particularly in scaled-down gate structures and charge storage mechanisms.
Innovation Solution
The implementation of a non-volatile memory structure that includes a substrate with tunnel insulating, charge storage, and blocking insulating patterns, along with a gate electrode, and the use of auxiliary structures like dummy mask patterns and assistant gate structures to mitigate these issues, ensuring effective charge storage and reduced leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If gate structure size is scaled down to increase memory density, then memory capacity increases, but short channel effect worsens
Solution Approach 1:
The gate structure is segmented into multiple gates (first gate and second gate) positioned at different locations. This segmentation allows independent control of different channel regions, enabling better electrostatic control and suppression of short channel effects while maintaining scaled dimensions for high density.
Solution Approach 2:
Different gate structures are applied to different regions of the memory device. First gates are positioned over first active regions while second gates are positioned over second active regions, allowing localized optimization of electrostatic control in different areas to mitigate short channel effects specific to each region's geometry.
2Quantity of substance
If charge storage pattern is made smaller to increase density, then memory capacity increases, but trap-assisted leakage current increases
Solution Approach 1:
An intermediate insulating layer is introduced between the charge storage pattern and the blocking insulating layer. This intermediate layer acts as a mediator that prevents direct interaction between trapped charges and the blocking layer, thereby suppressing trap-assisted leakage current while allowing the charge storage pattern to maintain small dimensions for high capacity.
3Ease of manufacture
If non-overlapped structure is used to simplify manufacturing, then manufacturing complexity decreases, but performance degradation increases
Solution Approach 1:
The invention uses a standardized gate electrode structure that can be repeatedly copied across different regions. The gate electrode is formed as a continuous pattern that can be replicated using standard photolithography and etching processes, maintaining manufacturing simplicity while ensuring consistent performance across all memory cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances device performance by minimizing the short channel effect and trap-assisted leakage current, leading to improved reliability and efficiency in memory operations.
Implementation Method 1
tunnel insulating pattern
Implementation Method 2
blocking insulating pattern
Data Source
AI summary
A memory transistor including a substrate, a tunnel insulating pattern on the substrate, a charge storage pattern on the tunnel insulating pattern, a blocking insulating pattern on the charge storage pattern, and a gate electrode on the blocking insulating pattern, the blocking insulating pattern surrounding the gate electrode and methods of operating and fabricating the same. A nonvolatile memory may further include a plurality of memory transistors in series and a plurality of auxiliary structures between each of the plurality of unit transistors in series. Each of the plurality of auxiliary structures may be a dummy mask pattern or an assistant gate structure.