3D Memory Gate Stack Doping for Reliable Erase Operation
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in simplifying the manufacturing process while achieving high integration and reliability, particularly in three-dimensional structures.
Innovation Solution
A semiconductor memory device with a gate stack structure, core pillar, channel layer, and doped semiconductor part, featuring a first region surrounding the core pillar and a second region extending between the memory layer and the core pillar, is manufactured through a method involving etching and doping processes to enhance junction overlap and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a three-dimensional stack structure is used to improve integration, then the degree of integration is improved, but the manufacturing process complexity increases
Solution Approach 1:
The manufacturing process is segmented into distinct stages: forming the gate stack structure, creating channel holes, depositing memory and channel layers, removing the substrate, and forming doped semiconductor parts. Each stage is independently optimized, allowing complex 3D structures to be built through manageable sequential steps rather than attempting to create the entire structure in one complex operation.
Solution Approach 2:
The gate stack structure, channel holes, memory layers, and channel layers are formed in advance before substrate removal. This preliminary formation of critical structures allows for precise control and optimization of each component independently, simplifying the overall manufacturing process by breaking down the complex task into preparatory steps that can be executed and verified before final assembly.
2Quantity of substance
If substrate removal is performed to expose memory layer for higher integration, then integration is improved, but manufacturing precision requirements increase
Solution Approach 1:
Doped semiconductor parts are formed in specific localized regions where precise electrical characteristics are needed, such as at the interfaces between memory layers and channel layers. This localized doping allows high precision to be applied only where critical, while other regions can be manufactured with standard precision requirements, thereby managing overall manufacturing complexity.
Solution Approach 2:
The patent replaces mechanical substrate support with a suspended membrane structure formed by substrate removal. This substitution allows the memory device to achieve higher integration by eliminating the need for a continuous substrate, enabling direct access to and manipulation of the memory layers from both sides, thereby improving manufacturing flexibility and precision in critical areas.
3Reliability
If doped semiconductor parts are formed to enhance junction overlap, then reliability is improved, but manufacturing process steps increase
Solution Approach 1:
The formation of doped semiconductor parts is merged with the existing manufacturing flow by utilizing the same etching and deposition equipment already used for creating channel holes and memory layers. The doping process is integrated into the sequence of layer formation operations, allowing junction overlap enhancement to be achieved without requiring entirely separate manufacturing equipment or processes, thereby limiting the increase in manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution simplifies the manufacturing process, improves integration, and enhances operational reliability by increasing gate-induced drain leakage efficiency in erase operations, thereby stabilizing the manufacturing process.
Implementation Method 1
forming a doped semiconductor part filling the recess region
Data Source
AI summary
A semiconductor memory device includes a gate stack structure including alternately stacked interlayer insulating layers and conductive layers, a core pillar penetrating the gate stack structure, a channel layer disposed between the core pillar and the gate stack structure, a memory layer disposed between the channel layer and the gate stack structure, and a doped semiconductor part in contact with the gate stack structure. The doped semiconductor part includes a first region surrounding the core pillar up to an interface in contact with the gate stack structure and a second region extending between the memory layer and the core pillar from the first region.