3D Memory Gate Stack Support Structure for Stress Distribution
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Solution Overview
Problem
The integration limits of two-dimensional nonvolatile memory devices have been reached, necessitating the development of three-dimensional structures, which face challenges in operational reliability due to stress distribution and structural integrity.
Innovation Solution
A semiconductor device with a gate stack structure and support structures that include alternately stacked interlayer insulating and conductive layers, featuring channel plugs and support structures with layers extending in different directions to distribute stress and enhance structural stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional nonvolatile memory devices are used to achieve simple manufacturing, then manufacturing ease is improved, but integration density deteriorates as integration limits are reached
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple memory cell layers are stacked along the vertical direction, with each layer containing bit lines, word lines, and memory regions arranged in three dimensions. This dimensional change enables significantly higher integration density while maintaining manufacturability through standardized stacking processes.
Solution Approach 2:
The patent implements nested structures where multiple functional layers are stacked within a vertical column. Memory cell layers are nested between interlayer insulating layers, with channel layers penetrating through multiple gate electrode layers. This nesting approach maximizes the use of vertical space to increase integration density without proportionally increasing manufacturing complexity.
2Quantity of substance
If three-dimensional stacked structures are implemented to increase integration density, then integration density is improved, but structural integrity and stress distribution deteriorate
Solution Approach 1:
The patent divides the three-dimensional stacked structure into multiple discrete layers including interlayer insulating layers, gate electrode layers, and memory cell layers. Each layer is separated and can be manufactured independently, allowing stress to be distributed across multiple interfaces rather than concentrated in a single structure. This segmentation maintains structural integrity while enabling high integration density.
Solution Approach 2:
The patent uses composite material structures combining different materials with complementary properties. Interlayer insulating layers provide mechanical support and stress distribution, while conductive layers provide electrical functionality. The combination of these materials creates a composite structure that maintains structural integrity under the stress of vertical stacking while achieving high integration density.
3Quantity of substance
If three-dimensional stacked structures are implemented to increase integration density, then integration density is improved, but stress distribution deteriorates
Solution Approach 1:
The patent segments the vertical stack into multiple thin layers separated by interlayer insulating layers. This segmentation distributes mechanical stress across multiple interfaces and prevents stress concentration that would occur in monolithic three-dimensional structures. Each layer can independently accommodate stress, maintaining overall structural stability while achieving high integration density.
Solution Approach 2:
The patent changes the physical parameters of the stacked structure by controlling layer thickness, material composition, and interface properties. By optimizing these parameters, the structure can accommodate thermal and mechanical stress while maintaining high integration density. The interlayer insulating layers are specifically designed with appropriate mechanical properties to distribute stress effectively.
Data Source
AI summary
There are provided a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a gate stack structure including a plurality of interlayer insulating layers and a plurality of conductive layers, which are alternately stacked in a third direction; a channel plug formed in a cell region, the channel plug penetrating the gate stack structure in the third direction; and at least one support structure formed in a contact region, the channel plug penetrating the gate stack structure in the third direction. The support structure includes a plurality of support structure layers that are sequentially stacked in the third direction, and the plurality of support structure layers are sequentially disposed such that each of the plurality of support structure layers extends in different directions along a plane defined by a first direction and a second direction, the first direction, the second direction, and the third direction being orthogonal to each other.