3D Nonvolatile Memory Gate Electrode Thickness Control
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Solution Overview
Problem
Conventional 3D nonvolatile memory devices face complexities in the deposition and etching processes due to differing thicknesses of gate electrode layers for selection transistors and memory cells, leading to increased off-leakage current and potential etching defects.
Innovation Solution
The solution involves alternately stacking interlayer dielectric and gate electrode layers over a substrate, with two or more gate electrode layers coupled to form selection transistors, ensuring uniform thickness and simplifying the process by using the same deposition equipment and reducing the need for additional masks during the slimming process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of gate electrode layers for selection transistors is increased to enhance off-leakage current characteristic, then the off-leakage current characteristic is improved, but the deposition process becomes complicated and process time increases
Solution Approach 1:
The patent applies local quality by forming gate electrode layers with different thicknesses at different locations: the first gate electrode layer has a first thickness in the first region (selection transistor region) and a second thickness in the second region (memory cell region), where the first thickness is greater than the second thickness. This allows the selection transistor to have enhanced off-leakage current characteristic while memory cells maintain standard characteristics, resolving the contradiction between improved reliability and reduced process complexity.
2Reliability
If the thickness of gate electrode layers for selection transistors is increased to enhance off-leakage current characteristic, then the off-leakage current characteristic is improved, but additional masks are required during slimming process
Solution Approach 1:
The patent implements local quality through spatially varying gate electrode layer thicknesses that are integrated into the standard slimming process flow. The first gate electrode layer is formed with greater thickness in the selection transistor region, and the existing slimming process selectively removes portions of gate electrode layers to create the stepped configuration. This approach achieves the required local differentiation without introducing additional masking steps, thereby maintaining ease of manufacture while improving reliability.
3Reliability
If different thicknesses of gate electrode layers are used for selection transistors and memory cells, then off-leakage current characteristic is enhanced, but the gate electrode layers must be deposited by different deposition equipments
Solution Approach 1:
The patent applies parameter changes by controlling the thickness of gate electrode layers deposited in a single continuous process. The first gate electrode layer is deposited with a first thickness in the first region and a second thickness in the second region, where the thickness parameter varies spatially across the substrate. This allows different effective gate thicknesses for selection transistors versus memory cells to be achieved using the same deposition equipment, eliminating the need for multiple deposition tools while enhancing off-leakage current characteristic.
Data Source
AI summary
A nonvolatile memory device includes a channel protruding in a vertical direction from a substrate, a plurality of interlayer dielectric layers and gate electrode layers which are alternately stacked over the substrate along the channel, and a memory layer formed between the channel and a stacked structure of the interlayer dielectric layers and gate electrode layers. Two or more gate electrode layers of the plurality of gate electrode layers are coupled to an interconnection line to form a selection transistor.