Memory Device Gray Code Programming Cell Distribution

Solution Overview

Problem

Existing memory devices face challenges in minimizing read voltage levels for multi-sensing operations and efficiently distributing read operations across logical pages, leading to suboptimal cell distribution and read timing performance.

Innovation Solution

A method and memory device that utilize a coding scheme to program memory cells by dividing elements into specific groups and allocating bit values in a gray code manner across multiple voltage levels, optimizing the distribution of read operations and minimizing read voltage levels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional programming methods are used, then programming simplicity is maintained, but read voltage levels are not minimized and cell distribution is suboptimal

Engineering Contradiction:
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent segments the programming process by dividing memory cells into different groups based on their voltage levels and programming states. This segmentation allows for optimized read voltage levels and improved cell distribution by treating different cell groups with tailored programming sequences, rather than applying a uniform programming approach to all cells.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes programming parameters dynamically based on cell state and group classification. By adjusting programming voltage levels, pulse widths, and sequencing according to the specific group being programmed, the system achieves optimal cell distribution and minimized read voltage levels while managing complexity through systematic parameter variation.

Inventive Principle:
Principle #35Parameter changes

2Duration of action of moving object

If read operations are concentrated on fewer voltage levels, then read timing is simplified, but multi-sensing operations require higher voltage levels

Engineering Contradiction:
Core Design Contradiction:
Duration of action of moving objectVSReliability

Solution Approach 1:

The patent introduces an additional dimension to read operations by implementing multi-sensing across multiple voltage levels rather than relying on a single voltage level. This dimensional expansion allows the system to distribute read operations across different voltage thresholds, improving timing characteristics while maintaining reliable detection through redundant sensing at multiple levels.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Manufacturing precision

If gray code allocation is applied to all elements, then cell distribution is optimized, but programming complexity increases

Engineering Contradiction:
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies gray code allocation selectively to specific segments or groups of memory cells rather than uniformly to all elements. This segmented approach to gray code implementation optimizes cell distribution within each group while reducing overall programming complexity by avoiding the need to manage gray code transitions across the entire memory array simultaneously.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10354723B2Memory device and method for programming the same
Publication Date: 2019.07.16
  • US10354723B2 patent drawing
  • US10354723B2 patent drawing
  • US10354723B2 patent drawing

AI summary

A memory device may include: a memory cell array including a plurality of memory cells; and a control circuit suitable for programming the memory cell array. The control circuit may program the memory cell array according to a predetermined coding method, such that read voltage levels for multi-sensing are minimized and the numbers of read operations for logical pages are distributed. Therefore, the memory device can improve the cell distribution for the plurality of memory cells and the performance of read timing.