Memory Controller Half-Rate Command Addressing for Signal Stability
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Solution Overview
Problem
Existing memory systems face challenges in stabilizing the transmission and reception of command and address signals due to increased loading, particularly in configurations where multiple memory chips are connected to a single memory controller, leading to signal quality deterioration.
Innovation Solution
Implementing a command address half rate mode that reduces the frequency of command address signals by half, using redivided multi-phase clocks to stabilize signal transmission and reception, and employing a memory controller with specific terminal connections and latency control circuits to manage operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple memory chips are connected to a single memory controller, then device density and integration are improved, but signal quality deteriorates due to increased loading
Solution Approach 1:
The patent changes the frequency parameter of command and address signals by introducing a half-rate mode that operates at half the normal frequency. This parameter change reduces the signal loading effect and stabilizes signal quality when multiple memory chips are connected to a single controller, while maintaining compatibility through mode selection mechanisms
2Speed
If command address signals are transmitted at high frequency, then data transmission speed is improved, but signal stability deteriorates due to increased loading
Solution Approach 1:
The patent implements a dynamic frequency adjustment mechanism where the command address signal frequency can be switched between normal rate and half-rate modes. This dynamic adaptation allows the system to optimize between transmission speed and signal stability based on the specific operating conditions and number of connected memory chips
Data Source
AI summary
A memory may include a clock receiver configured to receive clocks; a first divider configured to divide the clocks to generate divided multi-phase clocks; a second divider configured to redivide the divided multi-phase clocks to generate redivided multi-phase clocks; and a command address reception circuit configured to receive a command and an address by using the divided multi-phase clocks in a first mode, and receive the command and the address by using the redivided multi-phase clocks in a second mode.