Semiconductor Memory Hierarchical Bit Line Precharging
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor memory devices face high power consumption during read operations due to unnecessary precharging of local bit lines, leading to increased power usage and potential heat management issues.
Innovation Solution
A semiconductor memory device architecture that includes a memory cell array with hierarchized bit lines, where only the selected local bit line is precharged, and the global sense amplifier controls the potential on the second bit lines based on read data, reducing unnecessary precharging and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If local sense amplifiers precharge all local bit lines, then all memory cells can be accessed, but unnecessary local bit lines are precharged causing high power consumption
Solution Approach 1:
The patent divides the bit line hierarchy into local bit lines (first bit lines) and global bit lines (second bit lines). Local sense amplifiers are assigned to specific global bit lines and only precharge local bit lines connected to their assigned global bit line. This segmentation allows selective precharging of only necessary local bit lines, reducing power consumption while maintaining full memory cell accessibility through the hierarchical structure.
2Adaptability or versatility
If all local sense amplifiers are activated, then all global bit lines can be accessed, but unnecessary local sense amplifiers consume power
Solution Approach 1:
The patent implements local quality by assigning specific global bit lines to specific local sense amplifiers. Each local sense amplifier is responsible for a particular global bit line and only activates when that global bit line needs to be accessed. This localized responsibility ensures that only the necessary local sense amplifier and its associated local bit lines are precharged, reducing energy loss while maintaining the ability to access any global bit line through the appropriate local sense amplifier.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption during read operations by precharging only the necessary local bit line, enhancing efficiency and potentially lowering heat generation.
Implementation Method 1
MOS transistors, each having a floating gate and a control gate
Data Source
AI summary
A semiconductor memory device includes a memory cell array, first bit lines, second bit lines, first sense amplifiers and second sense amplifiers. The memory cell array includes memory cells arranged in a matrix. The first bit line connects commonly the memory cells in a same column. The second bit line connects commonly two or more of the first bit lines. The first sense amplifier is provided for the second bit line and controls not only the connection between the second bit lines and the first bit lines but also the potential on the second bit lines according to the data read from the memory cells onto the first bit lines. The second sense amplifier precharges the first bit line via the second bit line and the first sense amplifier and, when reading the data from the memory cells, amplifies the potential on the second bit lines.