3D Memory Cell Hole Layout for Channel Isolation Reliability
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Solution Overview
Problem
Existing three-dimensional semiconductor memory devices face challenges in improving operational reliability due to the limitations in the arrangement and connectivity of memory cells, which affect the efficiency and stability of data storage operations.
Innovation Solution
The semiconductor memory device incorporates a stack structure with conductive layers and butterfly-shaped holes, featuring memory layers and channel layers that enhance connectivity and isolation, allowing for improved channel layer formation and memory cell string definition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If channel layers are formed in closely spaced holes during manufacturing, then device density and integration are improved, but channel layers become vulnerable to damage and isolation failures
Solution Approach 1:
The patent applies preliminary action by forming the memory layer at the connection point between first and second hole parts before forming the channel layers. This pre-established memory layer creates an isolation barrier that protects the channel layers from damage during subsequent manufacturing processes, while still allowing high device density through closely spaced hole arrangement.
Solution Approach 2:
The memory layer positioned at the connection point between first and second hole parts serves as an intermediary structure. It physically separates and isolates the channel layers in adjacent holes, preventing direct interaction and potential damage between them, while maintaining the compact layout required for high density.
2Productivity
If holes are formed with narrow widths to increase storage capacity, then device integration is improved, but manufacturing precision requirements increase and damage risk increases
Solution Approach 1:
The patent applies local quality by positioning the memory layer specifically at the connection point between first and second hole parts, where it is most needed for isolation. The hole walls are selectively coated with the memory layer only in this critical region, providing enhanced precision control where required while maintaining narrower overall hole dimensions for high storage capacity.
3Productivity
If channel layers are placed close together to improve density, then device integration is improved, but isolation between channel layers becomes difficult
Solution Approach 1:
The patent forms the memory layer in advance at the connection point between hole parts before channel layer formation. This preliminary isolation structure simplifies the overall device complexity by pre-establishing the separation mechanism, allowing channel layers to be placed close together for high integration without requiring complex isolation structures to be added later.
Data Source
AI summary
There are provided a semiconductor memory device and a manufacturing method of a semiconductor memory device. The semiconductor memory device may include a stack structure including a plurality of conductive layers, a hole formed in the stack structure, a memory layer allowing a first part and a second part of the hole to be spaced apart from each other in the hole, and a first channel layer disposed in the first part of the hole and a second channel layer disposed in the second part of the hole.