Memory Hole Diameter Consistency via Mandrel Support

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Solution Overview

Problem

In semiconductor device manufacturing, the variation in memory hole diameter along the depth leads to variations in memory cell characteristics between upper and lower layers, affecting the performance and stability of memory cells.

Innovation Solution

A method involving alternately stacking insulating and electrode layers, forming holes through the multilayer body, depositing a conductive film on the hole's inner wall, anisotropically etching to leave the film on the sidewall, converting it into an insulator through heat treatment, and removing the insulator to expose electrode layers, ensuring consistent hole diameters and stable memory cell performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the number of stacked layers is increased to enhance memory capacity, then the memory device can store more data, but the aspect ratio of the memory hole becomes higher causing the sidewall to taper and the hole diameter to decrease toward the bottom

Engineering Contradiction:
Improvememory capacityVSAvoidhole diameter consistency
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

A mandrel structure is formed at the bottom of the memory hole before filling the charge storage layer. This preliminary structure serves as a support to maintain the hole diameter at the bottom region, preventing tapering effects when the number of stacked layers is increased. The mandrel allows the memory hole to maintain consistent dimensions throughout its depth, enabling higher memory capacity without sacrificing manufacturing precision.

Inventive Principle:
Principle #10Preliminary action

2Length of moving object

If the aspect ratio of the memory hole becomes higher, then more electrode layers can be stacked, but the sidewall becomes tapered and hole diameter varies along the depth

Engineering Contradiction:
Improvememory hole depthVSAvoidhole diameter uniformity
Core Design Contradiction:
Length of moving objectVSManufacturing precision

Solution Approach 1:

The mandrel structure is specifically positioned at the bottom of the memory hole where the tapering effect is most pronounced. This localized structural reinforcement addresses the specific region where diameter variation occurs, allowing the upper portions of the memory hole to maintain their intended dimensions while providing support where needed most.

Inventive Principle:
Principle #3Local quality

3Device complexity

If the hole diameter decreases toward the bottom of the memory hole, then the structure can accommodate more layers, but variation in hole diameter leads to variation in memory cell characteristics between upper and lower layers

Engineering Contradiction:
Improvenumber of stacked layersVSAvoidmemory cell characteristic consistency
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The mandrel is formed in advance at the bottom of the memory hole to establish a consistent diameter throughout the hole depth. This preliminary structural element ensures that both upper and lower memory cells experience the same geometric conditions, eliminating the diameter variation that would otherwise cause characteristic differences between cells at different heights.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach ensures consistent memory hole diameters, stabilizes memory cell characteristics, and prevents short-circuiting of electrode layers, resulting in a semiconductor device with improved reliability and performance.

Implementation Method 1

altering the conductive film into an insulator by heat treatment

Methodology Applied
Scientific EffectHeat treatment: Heat Treatment

Data Source

PatentUS8273628B2Semiconductor device manufacturing method including exposing electrode layers into a hole
Publication Date: 2012.09.25 KIOXIA CORP
  • US8273628B2 patent drawing
  • US8273628B2 patent drawing
  • US8273628B2 patent drawing

AI summary

A semiconductor device manufacturing method includes: alternately stacking a plurality of insulating layers and electrode layers; forming a hole penetrating through a multilayer body of the insulating layers and the electrode layers; forming a conductive film on an inner wall of the hole; anisotropically etching the conductive film to selectively leave the conductive film on a sidewall of the hole; altering the conductive film into an insulator by heat treatment; and removing the insulator covering the electrode layers to expose the electrode layers into the hole.