Memory Device Hydrogen Blocking Layer Annealing
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Solution Overview
Problem
Current methods for manufacturing memory devices with a cell on peripheral (COP) structure face challenges in integrating memory cells effectively without damaging them during the annealing process, which involves hydrogen and heat, essential for transistor formation.
Innovation Solution
The method involves forming a hydrogen supply layer and a hydrogen blocking layer on a lower interlayer insulating layer, followed by annealing to diffuse hydrogen and passivate transistor interfaces, then forming the memory cell on the hydrogen blocking layer after annealing, ensuring the memory cells are protected from hydrogen and heat.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If annealing process is performed to form transistor with hydrogen and heat, then transistor performance is improved, but memory cell may be damaged
Solution Approach 1:
A hydrogen supply layer is formed on the lower interlayer insulating layer before the annealing process. This layer provides hydrogen during annealing to improve transistor performance while preventing excessive hydrogen from reaching and damaging the memory cell, as the hydrogen supply layer acts as a controlled source that is consumed during the process.
Solution Approach 2:
A hydrogen blocking layer is formed between the hydrogen supply layer and the memory cell. This intermediate layer prevents hydrogen from reaching the memory cell during annealing, thereby protecting it from damage while still allowing the annealing process to proceed for transistor formation. The blocking layer mediates between the hydrogen supply and the memory cell.
2Ease of manufacture
If memory cell is formed before annealing, then manufacturing sequence is simplified, but memory cell is exposed to harmful hydrogen and heat
Solution Approach 1:
The hydrogen blocking layer is positioned between the annealing process and the memory cell, allowing the memory cell to be formed before annealing while still protecting it from harmful hydrogen and heat. This intermediary layer enables the simplified manufacturing sequence without compromising memory cell safety.
Solution Approach 2:
The harmful elements (hydrogen and heat) are extracted or blocked from reaching the memory cell by the hydrogen blocking layer, while the beneficial annealing process continues for transistor formation. This separation allows the memory cell to survive the annealing process.
3Reliability
If hydrogen supply layer is used to improve transistor characteristics, then transistor threshold voltage stability is enhanced, but hydrogen may reach and damage memory cell
Solution Approach 1:
The hydrogen blocking layer serves as a mediator that allows hydrogen to be supplied to the transistor region for threshold voltage stabilization while preventing hydrogen from reaching the memory cell. The blocking layer selectively permits hydrogen access to different regions.
Solution Approach 2:
The hydrogen blocking layer creates different hydrogen environments in different regions: the transistor region receives hydrogen for threshold voltage stabilization, while the memory cell region is protected from hydrogen. This local differentiation of hydrogen concentration achieves both goals.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces changes in threshold voltage of transistors, enhances the integration of memory cells, and prevents damage during the annealing process, allowing for the production of smaller, highly integrated memory devices.
Implementation Method 1
annealing the transistor, the lower interlayer insulating layer and the hydrogen supply layer
Implementation Method 2
annealing the transistor, the lower interlayer insulating layer and the hydrogen supply layer
Data Source
AI summary
A method of manufacturing a memory device includes forming a transistor on a substrate, forming a lower interlayer insulating layer covering the transistor, forming a hydrogen supply layer on the lower interlayer insulating layer, forming a hydrogen blocking layer on the hydrogen supply layer, annealing the transistor, the lower interlayer insulating layer, and the hydrogen supply layer, forming a memory cell on the hydrogen blocking layer after the annealing, and forming an upper interlayer insulating layer surrounding the memory cell and having a third average hydrogen concentration less than the second average hydrogen concentration.