3D Memory Interconnect Test Structures for Open Circuit Detection
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Solution Overview
Problem
The increasing density of memory cells in three-dimensional (3D) non-volatile memory devices makes it challenging to monitor the yield of interconnect structures, particularly as the aspect ratio of these structures increases, leading to issues such as open circuits due to their higher height-to-width ratio.
Innovation Solution
The implementation of test structures that emulate the interconnect structures within the 3D memory device, allowing for the accurate detection of electrical connections by serially coupling these test structures to identify any open circuits, thereby quickly identifying memory blocks with problematic electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the density of memory cells is increased in 3D non-volatile memory devices, then the storage capacity is improved, but the aspect ratio of interconnect structures increases leading to open circuits
Solution Approach 1:
The patent creates test structures that are copies of the actual interconnect structures within the 3D memory device. These test structures replicate the same geometry, materials, and fabrication processes, allowing them to experience the same reliability issues. By testing these identical copies, the patent can detect open circuits and other defects without needing to directly measure the difficult-to-access interconnect structures inside the memory device.
2Productivity
If the aspect ratio of interconnect structures is increased to achieve higher integration, then the degree of integration is improved, but the manufacturing precision deteriorates due to open circuits
Solution Approach 1:
The patent implements test structures during the fabrication process itself, integrating them alongside the actual memory device structures. This preliminary action allows defects in interconnect structures to be detected during manufacturing rather than after the device is completed. The test structures are formed using the same fabrication processes, so any manufacturing issues affecting high aspect ratio interconnects will be revealed when the test structures are measured.
3Measurement precision
If test structures are added to detect open circuits, then the measurement precision is improved, but the device complexity increases
Solution Approach 1:
The patent merges the test structures with the actual memory device structures, forming them as an integrated part of the device rather than adding separate external test equipment. The test structures share the same fabrication process, materials, and physical space as the memory cells and interconnect structures. This merging approach allows the test structures to be measured using standard characterization techniques already available for the memory device, avoiding the need for entirely new measurement systems.
Data Source
AI summary
A memory device includes a first memory block. The first memory block includes a first memory sub-array and a first interface portion disposed next to the first memory sub-array. The first interface portion has a plurality of first control structures formed as a first staircase profile. The first memory block further includes a plurality of first interconnect structures landing on a corresponding one of the plurality of first control structures, and a plurality of second interconnect structures configured to electrically couple a corresponding one of the plurality of first interconnect structures to a first transistor. The memory device further includes a first test structure and a second test structure disposed next to the first memory block, each configured to simulate electrical connections of the plurality of second interconnect structures. The first and second test structures are electrically coupled to each other and are electrically isolated form the first memory block.