Semiconductor Memory Interconnection Layer Segmentation
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Solution Overview
Problem
In semiconductor memory devices, the buried interconnection layer forms deeper grooves than bit line contacts, leading to increased junction leakage due to etching gas penetration and the dual damascene method used in forming the common source interconnection, which complicates the manufacturing process and affects device performance.
Innovation Solution
A semiconductor memory device design featuring a first and second interconnection layer configuration, where the second interconnection layer extends outside the first interconnection layer and is connected in a portion outside the semiconductor substrate, reducing the depth of the buried interconnection layer and minimizing junction leakage by altering the etching process and using interconnection portions to reduce resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the buried interconnection layer is formed using the dual damascene method, then the common source interconnection can be formed, but the groove for the buried interconnection layer becomes deeper than the holes for bit line contacts, increasing junction leakage
Solution Approach 1:
The interconnection structure is divided into two separate layers: a first interconnection layer (buried interconnection layer) formed in grooves between select transistors, and a second interconnection layer (common source line) formed on top of the first layer. This segmentation allows independent optimization of each layer's formation process and depth, preventing the buried interconnection layer from penetrating too deep into the semiconductor substrate.
Solution Approach 2:
The solution transitions from a single-layer vertical interconnection approach to a multi-layer three-dimensional structure. The second interconnection layer is formed at a higher vertical dimension above the first interconnection layer, allowing the common source interconnection to be established without requiring the buried interconnection layer to extend deeply into the substrate.
2Ease of manufacture
If etching gas is used to form grooves for the buried interconnection layer, then the groove can be formed, but the etching gas easily enters the groove and forms it deeper than necessary, increasing junction leakage
Solution Approach 1:
The groove formation process is segmented into two independent stages: first, grooves for the buried interconnection layer are formed to a controlled depth; second, grooves for the common source line are formed separately. This allows precise control of each groove's depth without the other interfering, preventing excessive etching into the substrate.
Solution Approach 2:
The grooves for the buried interconnection layer are formed in advance with controlled depth before forming the common source line grooves. This preliminary action establishes a depth reference that prevents subsequent over-etching, as the first layer's groove depth serves as a boundary that limits how deep the second layer's grooves can extend.
3Reliability
If the buried interconnection layer extends deeply into the substrate, then connection to the common source line is achieved, but junction leakage increases due to deeper penetration
Solution Approach 1:
The interconnection path is segmented into two distinct layers: the first interconnection layer provides the buried connection close to the substrate, while the second interconnection layer provides the common source line connection at a higher level. This segmentation allows electrical connection to be maintained while minimizing the depth of penetration into the substrate, thereby reducing junction leakage.
Solution Approach 2:
The first interconnection layer acts as an intermediary between the substrate and the second interconnection layer. It provides the initial connection point close to the substrate without requiring deep penetration, and the second interconnection layer serves as the mediator that extends the connection to the common source line region at a higher vertical level, reducing direct substrate interaction and junction leakage.
Data Source
AI summary
A semiconductor memory device includes a first block having first memory cells and first select transistors, a second block having second memory cells and second select transistors, and arranged adjacent to the first block in a first direction, the second select transistor being arranged to face the first select transistor and commonly having a diffusion region with the first select transistor, a first interconnection layer provided on the diffusion region between the first and second blocks and extending in a second direction, and a second interconnection layer having a first portion provided in contact with an upper portion of the first interconnection layer and extending to a portion outside the first interconnection layer, and a second portion extending in the second direction and connected to the first portion in a portion outside a portion on the first interconnection layer.