Memory Interface Boundary Scan for Low-Latency Connection Status
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Solution Overview
Problem
Existing methods for detecting faulty connections in memory device interfaces are unsuitable for deployed systems due to high latency and risk of data loss, particularly in critical applications like self-driving vehicles, where timely and reliable detection is essential.
Innovation Solution
Implementing a low-latency boundary scan technique that allows the host device to quickly determine the connection status by transmitting a same data pattern over two different sets of transmission lines, enabling the memory device to compare and indicate any faulty connections without suspending refresh operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing methods for detecting faulty connections are used, then connection status can be determined, but latency is high and data loss risk increases
Solution Approach 1:
The patent implements preliminary action by continuously monitoring interface connections using boundary scan technology before faults affect data integrity. The system proactively detects connection issues through dedicated scan circuits that independently verify transmission line integrity, allowing the system to respond to faults before they cause data loss or require costly recovery operations.
Solution Approach 2:
The patent introduces an intermediary boundary scan circuit as a mediator between the host device and memory device. This dedicated scan circuitry provides a separate, low-latency detection path that operates independently from normal data transmission channels, enabling fast connection status determination without interfering with primary memory operations or data flow.
2Reliability
If existing connection detection methods are implemented, then faulty connections can be identified, but refresh operations must be suspended causing productivity loss
Solution Approach 1:
The patent applies segmentation by dividing the detection function from the memory operation function. Boundary scan circuits are implemented as separate, dedicated detection hardware that operates independently from the main memory array and refresh control logic. This allows connection monitoring to occur in parallel with memory refresh operations, eliminating the need to suspend productivity-critical refresh tasks.
Solution Approach 2:
The patent ensures continuity of useful action by designing the boundary scan mechanism to operate continuously alongside normal memory operations. The scan circuits monitor transmission lines without interrupting refresh cycles or data access, maintaining uninterrupted memory throughput while providing ongoing connection verification through dedicated detection resources.
3Loss of time
If fast connection detection is implemented, then latency is reduced, but system complexity increases
Solution Approach 1:
The patent uses copying by replicating simple boundary scan circuitry at both the host device and memory device ends of the interface. These copied scan circuits provide fast detection capability through standardized, pre-designed modules that can be integrated into existing systems. The replication of detection logic at both ends enables bidirectional verification without requiring complex centralized control mechanisms.
Data Source
AI summary
Methods, systems, and devices for techniques for determining an interface connection status are described. A system may include an interface between a host device and a memory device. The host device may transmit to the memory device first data in a pattern over a first set of transmission lines of the interface. The host device may also transmit to the memory device second data in the pattern over a second set of transmission lines of the interface. The memory device may compare the first data and the second data, and based on the comparison, send an indication of a connection status of the interface to the host device.