Memory Die Interface Segmentation for Processing Die Access
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Solution Overview
Problem
Current communication interfaces between processing and memory dies in 2.5D semiconductor devices are inefficient, as they require all ASIC dies to access the entire HBM die, leading to unnecessary complexity and increased fabrication costs, especially when only a subset of channels are needed.
Innovation Solution
The communication interface structure splits the interface edge of the memory die into multiple groups, allowing multiple ASIC dies to access the memory die through interposer or RDL layers, with interconnection routings connecting each processing die to specific interface groups, enabling flexible access and reducing fabrication complexity and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If all ASIC dies are connected to the entire HBM die interface, then comprehensive access capability is achieved, but device complexity and fabrication cost increase
Solution Approach 1:
The HBM die interface is divided into multiple interface groups (e.g., first interface group, second interface group), and each ASIC die is connected to only the specific interface group(s) it needs. This segmentation allows selective access to memory channels, reducing unnecessary connections and simplifying the overall interface structure while maintaining adaptability for different ASIC requirements.
2Productivity
If all ASIC dies access the entire HBM die, then full bandwidth is available, but fabrication cost increases
Solution Approach 1:
The interface is segmented into multiple groups, allowing fabrication processes to be optimized for each group independently. ASIC dies requiring full bandwidth can access multiple interface groups, while those needing less bandwidth access only specific groups, reducing the number of required connections and lowering fabrication costs.
Solution Approach 2:
Different interface groups can be designed with different qualities or capacities based on local requirements. Interface groups connected to high-performance ASICs can have higher bandwidth capabilities, while groups connected to lower-performance ASICs can have reduced capabilities, optimizing overall system performance and reducing fabrication costs.
3Adaptability or versatility
If the interface structure supports multiple ASIC dies with different functionalities, then system versatility improves, but interface design complexity increases
Solution Approach 1:
The interface structure is designed with universal interface groups that can serve multiple ASIC dies with different functionalities. Each interface group is designed to be compatible with various ASIC types, allowing the same HBM die to support diverse applications (e.g., graphics processing, AI computing, general-purpose computing) without requiring custom interface designs for each ASIC type.
Data Source
AI summary
A communication interface structure for connection between dies is provided, including a memory die, processing dies and interconnection routings. The memory die includes a first interface edge, wherein the first interface edge is split into a plurality of interface groups. Each of the processing dies includes a second interface edge. Interconnection routings respectively connect the second interface edges of the processing dies to the interface groups of the memory die.